From: Hitesh K. Patel <[email protected]> dynamically enable/disable the alpha channel of display Plane A
Signed-off-by: John Ye <[email protected]> Signed-off-by: Hitesh K. Patel <[email protected]> --- drivers/staging/mrst/drv/psb_intel_display2.c | 23 ++++++++++++++++++++ .../services4/srvkm/bridged/bridged_pvr_bridge.c | 13 +++++++++++ 2 files changed, 36 insertions(+), 0 deletions(-) diff --git a/drivers/staging/mrst/drv/psb_intel_display2.c b/drivers/staging/mrst/drv/psb_intel_display2.c index 9951673..714ff01 100644 --- a/drivers/staging/mrst/drv/psb_intel_display2.c +++ b/drivers/staging/mrst/drv/psb_intel_display2.c @@ -315,6 +315,27 @@ const struct drm_crtc_funcs mdfld_intel_crtc_funcs = { .destroy = psb_intel_crtc_destroy, }; +static struct drm_device globle_dev; + +void mdfld__intel_plane_set_alpha(int enable) +{ + struct drm_device *dev = &globle_dev; + int dspcntr_reg = DSPACNTR; + u32 dspcntr; + + dspcntr = REG_READ(dspcntr_reg); + + if (enable) { + dspcntr &= ~DISPPLANE_32BPP_NO_ALPHA; + dspcntr |= DISPPLANE_32BPP; + } else { + dspcntr &= ~DISPPLANE_32BPP; + dspcntr |= DISPPLANE_32BPP_NO_ALPHA; + } + + REG_WRITE(dspcntr_reg, dspcntr); +} + int mdfld__intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *old_fb) { struct drm_device *dev = crtc->dev; @@ -331,6 +352,8 @@ int mdfld__intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, struct drm_f u32 dspcntr; int ret = 0; + memcpy(&globle_dev, dev, sizeof(struct drm_device)); + PSB_DEBUG_ENTRY("pipe = 0x%x. \n", pipe); /* no fb bound */ diff --git a/drivers/staging/mrst/pvr/services4/srvkm/bridged/bridged_pvr_bridge.c b/drivers/staging/mrst/pvr/services4/srvkm/bridged/bridged_pvr_bridge.c index 17fa61f..49687bc 100644 --- a/drivers/staging/mrst/pvr/services4/srvkm/bridged/bridged_pvr_bridge.c +++ b/drivers/staging/mrst/pvr/services4/srvkm/bridged/bridged_pvr_bridge.c @@ -2130,6 +2130,8 @@ PVRSRVSetDCSrcRectBW(IMG_UINT32 ui32BridgeID, return 0; } +extern void mdfld__intel_plane_set_alpha(int enable); + static IMG_INT PVRSRVSetDCDstColourKeyBW(IMG_UINT32 ui32BridgeID, PVRSRV_BRIDGE_IN_SET_DISPCLASS_COLOURKEY *psSetDispClassColKeyIN, @@ -2141,6 +2143,17 @@ PVRSRVSetDCDstColourKeyBW(IMG_UINT32 ui32BridgeID, PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SET_DISPCLASS_DSTCOLOURKEY); + /* XXX this is a workaround, will have a formal implementation later on */ + if ((IMG_UINT32)psSetDispClassColKeyIN->hSwapChain == 0xC0C0C0C0) { + if ( (IMG_UINT32)psSetDispClassColKeyIN->ui32CKColour == 0xD0D0D0D0) { + mdfld__intel_plane_set_alpha(IMG_TRUE); + } else if ((IMG_UINT32)psSetDispClassColKeyIN->ui32CKColour == 0xE0E0E0E0) { + mdfld__intel_plane_set_alpha(IMG_FALSE); + } + psRetOUT->eError = PVRSRV_OK; + return 0; + } + psRetOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase, &pvDispClassInfo, -- 1.7.1 _______________________________________________ MeeGo-kernel mailing list [email protected] http://lists.meego.com/listinfo/meego-kernel
