From: Rajesh Poornachandran <[email protected]>
Medfield Runtim PM Support with DSR
Note:
- Panel would be ON and in DSR during S0i3. Panel will get turned OFF on X
screen saver timeout.
- GFX PCI D3 will happen once value in /proc/dri/0/rtpm expires.
- This value can be set to 10/20/30 secs by doing echo 1/2/3 into
/proc/dri/0/rtpm.
- Current value can be read via "cat /proc/dri/0/rtpm"
Signed-off-by: Rajesh Poornachandran <[email protected]>
Signed-off-by: Hitesh K. Patel <[email protected]>
---
drivers/staging/mrst/drv/mdfld_dsi_dbi.c | 21 +++++
drivers/staging/mrst/drv/psb_drv.c | 48 +++++++++++-
drivers/staging/mrst/drv/psb_drv.h | 1 +
drivers/staging/mrst/drv/psb_intel_display2.c | 23 ++++--
drivers/staging/mrst/drv/psb_intel_reg.h | 3 +
drivers/staging/mrst/drv/psb_powermgmt.c | 83 ++++++++++++++++---
drivers/staging/mrst/drv/psb_reg.h | 6 +-
.../mrst/pvr/services4/system/unified/sysconfig.c | 2 +-
8 files changed, 160 insertions(+), 27 deletions(-)
diff --git a/drivers/staging/mrst/drv/mdfld_dsi_dbi.c
b/drivers/staging/mrst/drv/mdfld_dsi_dbi.c
index 45d8030..eff8976 100644
--- a/drivers/staging/mrst/drv/mdfld_dsi_dbi.c
+++ b/drivers/staging/mrst/drv/mdfld_dsi_dbi.c
@@ -33,6 +33,8 @@
extern int allow_runtime_pm;
extern struct drm_device *gpDrmDevice;
+bool bindsr = false;
+extern int gfxrtdelay;
/**
* set refreshing area
*/
@@ -407,6 +409,18 @@ void mdfld_dsi_dbi_enter_dsr (struct mdfld_dsi_dbi_output
* dbi_output, int pipe
/*update mode state to IN_DSR*/
dbi_output->mode_flags |= MODE_SETTING_IN_DSR;
+
+#ifdef CONFIG_PM_RUNTIME
+ //Runtime PM
+ if(allow_runtime_pm && pipe == 2){
+ int ret = 0;
+ ret = pm_schedule_suspend(&gpDrmDevice->pdev->dev, gfxrtdelay);
+ if(ret)
+ WARN(1, "FIXME-RAJESH: %s ret code: %d \n", __func__,
ret);
+ bindsr = true;
+ }
+#endif
+
}
#ifndef CONFIG_MDFLD_DSI_DPU
@@ -421,6 +435,13 @@ static void mdfld_dbi_output_exit_dsr (struct
mdfld_dsi_dbi_output * dbi_output,
u32 dspcntr_reg = DSPACNTR;
u32 reg_offset = 0;
+#ifdef CONFIG_PM_RUNTIME
+ //Runtime PM
+ if(allow_runtime_pm){
+ bindsr = false;
+ }
+#endif
+
/*if mode setting on-going, back off*/
if((dbi_output->mode_flags & MODE_SETTING_ON_GOING) ||
(psb_crtc && psb_crtc->mode_flags & MODE_SETTING_ON_GOING))
diff --git a/drivers/staging/mrst/drv/psb_drv.c
b/drivers/staging/mrst/drv/psb_drv.c
index a744e32..c07225b 100644
--- a/drivers/staging/mrst/drv/psb_drv.c
+++ b/drivers/staging/mrst/drv/psb_drv.c
@@ -78,6 +78,7 @@ int drm_topaz_pmpolicy = PSB_PMPOLICY_NOPM;
int drm_topaz_sbuswa;
int drm_psb_ospm = 1;
int drm_psb_topaz_clockgating = 0;
+int gfxrtdelay = 2 * 1000;
static int PanelID = GCT_DETECT;
static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
@@ -89,6 +90,7 @@ MODULE_PARM_DESC(disable_vsync, "Disable vsync interrupts");
MODULE_PARM_DESC(force_pipeb, "Forces PIPEB to become primary fb");
MODULE_PARM_DESC(ta_mem_size, "TA memory size in kiB");
MODULE_PARM_DESC(ospm, "switch for ospm support");
+MODULE_PARM_DESC(rtpm, "Specifies Runtime PM delay for GFX");
MODULE_PARM_DESC(msvdx_pmpolicy, "msvdx power management policy btw frames");
MODULE_PARM_DESC(topaz_pmpolicy, "topaz power managerment policy btw frames");
MODULE_PARM_DESC(topaz_sbuswa, "WA for topaz sysbus write");
@@ -101,6 +103,7 @@ module_param_named(msvdx_command_delay, drm_msvdx_delay,
int, 0600);
module_param_named(topaz_pmpolicy, drm_topaz_pmpolicy, int, 0600);
module_param_named(topaz_sbuswa, drm_topaz_sbuswa, int, 0600);
module_param_named(ospm, drm_psb_ospm, int, 0600);
+module_param_named(rtpm, gfxrtdelay, int, 0600);
module_param_named(topaz_clockgating, drm_psb_topaz_clockgating, int, 0600);
#ifndef MODULE
/* Make ospm configurable via cmdline firstly, and others can be enabled if
needed. */
@@ -2659,6 +2662,44 @@ static int psb_blc_read(char *buf, char **start, off_t
offset, int request,
return len - offset;
}
+static int psb_rtpm_read(char *buf, char **start, off_t offset, int request,
+ int *eof, void *data)
+{
+ printk(KERN_ALERT "Current Runtime PM delay for GFX: %d (ms) \n",
gfxrtdelay);
+
+ return 0;
+}
+
+static int psb_rtpm_write(struct file *file, const char *buffer,
+ unsigned long count, void *data)
+{
+ char buf[2];
+ int temp = 0;
+ if (count != sizeof(buf)) {
+ return -EINVAL;
+ } else {
+ if (copy_from_user(buf, buffer, count))
+ return -EINVAL;
+ if (buf[count-1] != '\n')
+ return -EINVAL;
+ temp = buf[0] - '0';
+ switch(temp){
+ case 1:
+ gfxrtdelay = 10 * 1000;
+ break;
+
+ case 2:
+ gfxrtdelay = 20 * 1000;
+ break;
+ default:
+ gfxrtdelay = 30 * 1000;
+ break;
+ }
+ printk(KERN_ALERT "Runtime PM delay set for GFX: %d (ms) \n",
gfxrtdelay);
+ }
+ return count;
+}
+
static int psb_ospm_read(char *buf, char **start, off_t offset, int request,
int *eof, void *data)
{
@@ -2762,21 +2803,26 @@ static int psb_proc_init(struct drm_minor *minor)
{
struct proc_dir_entry *ent;
struct proc_dir_entry *ent1;
+ struct proc_dir_entry *rtpm;
ent = create_proc_entry(OSPM_PROC_ENTRY, 0644, minor->proc_root);
+ rtpm = create_proc_entry(RTPM_PROC_ENTRY, 0644, minor->proc_root);
ent1 = create_proc_read_entry(BLC_PROC_ENTRY, 0, minor->proc_root,
psb_blc_read, minor);
- if (!ent || !ent1)
+ if (!ent || !ent1 || !rtpm)
return -1;
ent->read_proc = psb_ospm_read;
ent->write_proc = psb_ospm_write;
ent->data = (void *)minor;
+ rtpm->read_proc = psb_rtpm_read;
+ rtpm->write_proc = psb_rtpm_write;
return 0;
}
static void psb_proc_cleanup(struct drm_minor *minor)
{
remove_proc_entry(OSPM_PROC_ENTRY, minor->proc_root);
+ remove_proc_entry(RTPM_PROC_ENTRY, minor->proc_root);
remove_proc_entry(BLC_PROC_ENTRY, minor->proc_root);
return;
}
diff --git a/drivers/staging/mrst/drv/psb_drv.h
b/drivers/staging/mrst/drv/psb_drv.h
index 02efbdd..d61532c 100644
--- a/drivers/staging/mrst/drv/psb_drv.h
+++ b/drivers/staging/mrst/drv/psb_drv.h
@@ -85,6 +85,7 @@ enum panel_type {
#define DRIVER_DESC "drm driver for the Intel GMA500"
#define DRIVER_AUTHOR "Intel Corporation"
#define OSPM_PROC_ENTRY "ospm"
+#define RTPM_PROC_ENTRY "rtpm"
#define BLC_PROC_ENTRY "mrst_blc"
#define PSB_DRM_DRIVER_DATE "2009-03-10"
diff --git a/drivers/staging/mrst/drv/psb_intel_display2.c
b/drivers/staging/mrst/drv/psb_intel_display2.c
index bcdda91..e4e8017 100644
--- a/drivers/staging/mrst/drv/psb_intel_display2.c
+++ b/drivers/staging/mrst/drv/psb_intel_display2.c
@@ -37,6 +37,7 @@ extern int allow_runtime_pm;
extern struct drm_device *gpDrmDevice;
extern void mdfld_save_display(struct drm_device *dev);
+
/* MDFLD_PLATFORM start */
void mdfldWaitForPipeDisable(struct drm_device *dev, int pipe)
{
@@ -733,20 +734,23 @@ static void mdfld_crtc_dpms(struct drm_crtc *crtc, int
mode)
if it's on this pipe */
/* psb_intel_crtc_dpms_video(crtc, true); TODO */
+#ifdef CONFIG_PM_RUNTIME
//Runtime PM
- if(allow_runtime_pm){
- dev_priv->is_mipi_on = true;
- }
+ if(allow_runtime_pm){
+ dev_priv->is_mipi_on = true;
+ }
+#endif
break;
case DRM_MODE_DPMS_OFF:
/* Give the overlay scaler a chance to disable
* if it's on this pipe */
/* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
-
- //Runtime PM
+#ifdef CONFIG_PM_RUNTIME
+ //Runtime PM
if(allow_runtime_pm && dev_priv->is_mipi_on && pipe == 0)
- mdfld_save_display(gpDrmDevice);
+ mdfld_save_display(gpDrmDevice);
+#endif
if (pipe != 1)
mdfld_dsi_gen_fifo_ready (dev, gen_fifo_stat_reg,
HS_CTRL_FIFO_EMPTY | HS_DATA_FIFO_EMPTY);
@@ -801,12 +805,13 @@ static void mdfld_crtc_dpms(struct drm_crtc *crtc, int
mode)
#endif /* MDFLD_PO_JLIU7 */
}
}
-
- //Runtime PM
+#ifdef CONFIG_PM_RUNTIME
+ //Runtime PM
if(allow_runtime_pm && pipe == 1){
dev_priv->is_mipi_on = false;
- pm_request_idle(&gpDrmDevice->pdev->dev);
+ //pm_request_idle(&gpDrmDevice->pdev->dev);
}
+#endif
break;
}
diff --git a/drivers/staging/mrst/drv/psb_intel_reg.h
b/drivers/staging/mrst/drv/psb_intel_reg.h
index c95da7d..1e9af71 100644
--- a/drivers/staging/mrst/drv/psb_intel_reg.h
+++ b/drivers/staging/mrst/drv/psb_intel_reg.h
@@ -811,6 +811,9 @@ Ignore alpha.1110 = 32 - bit RGBX(8 : 8 : 8 : 8) pixel
format.
;--------------------------------------------------------------------------*/
#define MIPIC_REG_OFFSET 0x800
#define DEVICE_READY_REG 0xb000
+#define LP_OUTPUT_HOLD BIT16
+#define EXIT_ULPS_DEV_READY 0x3
+#define LP_OUTPUT_HOLD_RELEASE 0x810000
# define ENTERING_ULPS (2 << 1)
# define EXITING_ULPS (1 << 1)
# define ULPS_MASK (3 << 1)
diff --git a/drivers/staging/mrst/drv/psb_powermgmt.c
b/drivers/staging/mrst/drv/psb_powermgmt.c
index ca0a87f..3abf30f 100644
--- a/drivers/staging/mrst/drv/psb_powermgmt.c
+++ b/drivers/staging/mrst/drv/psb_powermgmt.c
@@ -45,6 +45,7 @@ extern IMG_UINT32 gui32SGXDeviceID;
extern IMG_UINT32 gui32MRSTDisplayDeviceID;
extern IMG_UINT32 gui32MRSTMSVDXDeviceID;
extern IMG_UINT32 gui32MRSTTOPAZDeviceID;
+extern bool bindsr;
struct drm_device *gpDrmDevice = NULL;
static struct mutex g_ospm_mutex;
@@ -986,6 +987,9 @@ static int mdfld_save_cursor_overlay_registers(struct
drm_device *dev)
*/
static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
{
+ //to get panel out of ULPS mode.
+ u32 temp = 0;
+ u32 device_ready_reg = DEVICE_READY_REG;
int ret = 0;
struct drm_psb_private *dev_priv = dev->dev_private;
struct mdfld_dsi_dbi_output * dsi_output = dev_priv->dbi_output;
@@ -1224,13 +1228,36 @@ static int mdfld_restore_display_registers(struct
drm_device *dev, int pipe)
msleep(20);
+ /* LP Hold Release */
+ temp = REG_READ(mipi_reg);
+ temp |= LP_OUTPUT_HOLD_RELEASE;
+ REG_WRITE(mipi_reg, temp);
+ mdelay(1);
+
+
+ /* Set DSI host to exit from Utra Low Power State */
+ temp = REG_READ(device_ready_reg);
+ temp &= ~ULPS_MASK;
+ temp |= 0x3;
+ temp |= EXIT_ULPS_DEV_READY;
+ REG_WRITE(device_ready_reg, temp);
+ mdelay(1);
+
+ temp = REG_READ(device_ready_reg);
+ temp &= ~ULPS_MASK;
+ temp |= EXITING_ULPS;
+ REG_WRITE(device_ready_reg, temp);
+ mdelay(1);
+
+#if 0
+
/*send exit_sleep_mode DCS*/
ret = mdfld_dsi_dbi_send_dcs(dsi_output, exit_sleep_mode, NULL, 0,
CMD_DATA_SRC_SYSTEM_MEM);
if(ret) {
DRM_ERROR("%s, sent exit_sleep_mode faild. \n", __FUNCTION__);
return -EINVAL;
}
-
+#endif
if (dev_priv->platform_rev_id != MDFLD_PNW_A0) {
/*send set_tear_on DCS*/
ret = mdfld_dsi_dbi_send_dcs(dsi_output, set_tear_on, ¶m,
1, CMD_DATA_SRC_SYSTEM_MEM);
@@ -1260,12 +1287,14 @@ static int mdfld_restore_display_registers(struct
drm_device *dev, int pipe)
return -EINVAL;
}
+#if 0
/*send set_display_on DCS*/
ret = mdfld_dsi_dbi_send_dcs(dsi_output, set_display_on, NULL, 0,
CMD_DATA_SRC_SYSTEM_MEM);
if(ret) {
DRM_ERROR("%s, sent set_display_on faild. \n", __FUNCTION__);
return -EINVAL;
}
+#endif
if (dev_priv->platform_rev_id != MDFLD_PNW_A0) {
@@ -1338,7 +1367,9 @@ static int mdfld_restore_cursor_overlay_registers(struct
drm_device *dev)
*/
void mdfld_save_display(struct drm_device *dev)
{
+#ifdef OSPM_GFX_DPK
printk(KERN_ALERT "ospm_save_display\n");
+#endif
mdfld_save_cursor_overlay_registers(dev);
@@ -1363,6 +1394,10 @@ void ospm_suspend_display(struct drm_device *dev)
struct mdfld_dbi_dsr_info * dsr_info = dev_priv->dbi_dsr_info;
struct timer_list * dsr_timer = &dsr_info->dsr_timer;
#endif
+ //to put panel into ULPS mode.
+ u32 temp = 0;
+ u32 device_ready_reg = DEVICE_READY_REG;
+ u32 mipi_reg = MIPI;
if (!(g_hw_power_status_mask & OSPM_DISPLAY_ISLAND))
return;
@@ -1386,8 +1421,11 @@ void ospm_suspend_display(struct drm_device *dev)
if(dev_priv->is_mipi_on){
mdfld_save_display_registers(dev, 0);
+//Put the panel in ULPS mode; don't turn OFF during S0ix.
+#if 0
if (mdfld_dsi_dbi_update_power(dev_priv->dbi_output,
DRM_MODE_DPMS_OFF))
DRM_ERROR("%s, can't disable dbi_0 panel. \n",
__FUNCTION__);
+#endif
}
@@ -1395,8 +1433,11 @@ void ospm_suspend_display(struct drm_device *dev)
if(dev_priv->is_mipi_on){
mdfld_save_display_registers(dev, 2);
+//Put the panel in ULPS mode; don't turn OFF during S0ix.
+#if 0
if (mdfld_dsi_dbi_update_power(dev_priv->dbi_output2,
DRM_MODE_DPMS_OFF))
DRM_ERROR("%s, can't disable dbi_2 panel. \n",
__FUNCTION__);
+#endif
}
@@ -1421,6 +1462,18 @@ void ospm_suspend_display(struct drm_device *dev)
}
#endif
+ /* Put the panel in ULPS mode for S0ix. */
+ temp = REG_READ(device_ready_reg);
+ temp &= ~ULPS_MASK;
+ temp |= ENTERING_ULPS;
+ REG_WRITE(device_ready_reg, temp);
+
+ //LP Hold
+ temp = REG_READ(mipi_reg);
+ temp &= ~LP_OUTPUT_HOLD;
+ REG_WRITE(mipi_reg, temp);
+ mdelay(1);
+
} else {
save_display_registers(dev);
@@ -1548,7 +1601,9 @@ static void ospm_suspend_pci(struct pci_dev *pdev)
if (gbSuspended)
return;
- /*printk(KERN_ALERT "ospm_suspend_pci\n");*/
+#ifdef OSPM_GFX_DPK
+ printk(KERN_ALERT "ospm_suspend_pci\n");
+#endif
#ifdef CONFIG_MDFD_GL3
// Power off GL3 after all GFX sub-systems are powered off.
@@ -1584,7 +1639,9 @@ static bool ospm_resume_pci(struct pci_dev *pdev)
if (!gbSuspended)
return true;
- /*printk(KERN_ALERT "ospm_resume_pci\n");*/
+#ifdef OSPM_GFX_DPK
+ printk(KERN_ALERT "ospm_resume_pci\n");
+#endif
pci_set_power_state(pdev, PCI_D0);
pci_restore_state(pdev);
@@ -1769,7 +1826,7 @@ void ospm_power_island_up(int hw_islands)
if (dev_priv->platform_rev_id != MDFLD_PNW_A0)
pwr_mask = MDFLD_PWRGT_DISPLAY_STS_B0;
else
- pwr_mask = MDFLD_PWRGT_DISPLAY_STS;
+ pwr_mask = MDFLD_PWRGT_DISPLAY_STS_A0;
}
while (true) {
@@ -1891,7 +1948,7 @@ void ospm_power_island_down(int islands)
if (dev_priv->platform_rev_id != MDFLD_PNW_A0)
pwr_mask = MDFLD_PWRGT_DISPLAY_STS_B0;
else
- pwr_mask = MDFLD_PWRGT_DISPLAY_STS;
+ pwr_mask = MDFLD_PWRGT_DISPLAY_STS_A0;
}
while (true) {
@@ -1947,6 +2004,10 @@ bool ospm_power_using_hw_begin(int hw_island, UHBUsage
usage)
return false;
else {
locked = false;
+#ifdef CONFIG_PM_RUNTIME
+ /* increment pm_runtime_refcount */
+ pm_runtime_get(&pdev->dev);
+#endif
goto increase_count;
}
}
@@ -2064,8 +2125,6 @@ increase_count:
atomic_inc(&g_display_access_count);
break;
}
- /* increment pm_runtime_refcount */
- pm_runtime_get(&pdev->dev);
}
if (!b_atomic && locked)
@@ -2110,7 +2169,6 @@ void ospm_power_using_hw_end(int hw_island)
}
int psb_runtime_suspend(struct device *dev)
{
- struct drm_psb_private* dev_priv = gpDrmDevice->dev_private;
pm_message_t state;
int ret = 0;
state.event = 0;
@@ -2120,11 +2178,11 @@ int psb_runtime_suspend(struct device *dev)
#endif
if (atomic_read(&g_graphics_access_count) ||
atomic_read(&g_videoenc_access_count)
|| atomic_read(&g_videodec_access_count) ||
atomic_read(&g_display_access_count)
- || dev_priv->is_mipi_on ){
+ || (bindsr == false) ){
#ifdef OSPM_GFX_DPK
- printk(KERN_ALERT "OSPM_GFX_DPK: GFX: %d VEC: %d VED: %d DC:
%d MIPI: %d \n", atomic_read(&g_graphics_access_count),
+ printk(KERN_ALERT "OSPM_GFX_DPK: GFX: %d VEC: %d VED: %d DC:
%d DSR: %d \n", atomic_read(&g_graphics_access_count),
atomic_read(&g_videoenc_access_count),
atomic_read(&g_videodec_access_count), atomic_read(&g_display_access_count),
- dev_priv->is_mipi_on);
+ bindsr?1:0);
#endif
return -EBUSY;
}
@@ -2142,7 +2200,6 @@ int psb_runtime_resume(struct device *dev)
int psb_runtime_idle(struct device *dev)
{
- struct drm_psb_private* dev_priv = gpDrmDevice->dev_private;
#if 1
int msvdx_hw_busy = 0;
int topaz_hw_busy = 0;
@@ -2153,7 +2210,7 @@ int psb_runtime_idle(struct device *dev)
/*printk (KERN_ALERT "lvds:%d,mipi:%d\n", dev_priv->is_lvds_on,
dev_priv->is_mipi_on);*/
if (atomic_read(&g_graphics_access_count) ||
atomic_read(&g_videoenc_access_count)
|| atomic_read(&g_videodec_access_count) ||
atomic_read(&g_display_access_count)
- || dev_priv->is_lvds_on || dev_priv->is_mipi_on
+ || (bindsr == false)
#if 1
|| (msvdx_hw_busy == 1)
|| (topaz_hw_busy == 1))
diff --git a/drivers/staging/mrst/drv/psb_reg.h
b/drivers/staging/mrst/drv/psb_reg.h
index cbe5405..d80b4f3 100644
--- a/drivers/staging/mrst/drv/psb_reg.h
+++ b/drivers/staging/mrst/drv/psb_reg.h
@@ -572,7 +572,7 @@
#define MDFLD_PWRGT_DISPLAY_B_CNTR 0x0000c000
#define MDFLD_PWRGT_DISPLAY_C_CNTR 0x00030000
#define MDFLD_PWRGT_DISP_MIPI_CNTR 0x000c0000
-#define MDFLD_PWRGT_DISPLAY_CNTR (MDFLD_PWRGT_DISPLAY_A_CNTR |
MDFLD_PWRGT_DISPLAY_C_CNTR)// 0x000fc00c
+#define MDFLD_PWRGT_DISPLAY_CNTR (MDFLD_PWRGT_DISPLAY_A_CNTR |
MDFLD_PWRGT_DISPLAY_B_CNTR | MDFLD_PWRGT_DISPLAY_C_CNTR |
MDFLD_PWRGT_DISP_MIPI_CNTR)// 0x000fc00c
// Display SSS register bits are different in A0 vs. B0
#define PSB_PWRGT_GFX_MASK 0x3
#define MDFLD_PWRGT_DISPLAY_A_STS 0x000000c0
@@ -583,6 +583,6 @@
#define MDFLD_PWRGT_DISPLAY_B_STS_B0 0x0000c000
#define MDFLD_PWRGT_DISPLAY_C_STS_B0 0x00030000
#define MDFLD_PWRGT_DISP_MIPI_STS 0x000c0000
-#define MDFLD_PWRGT_DISPLAY_STS (MDFLD_PWRGT_DISPLAY_A_STS |
MDFLD_PWRGT_DISPLAY_C_STS)// 0x000fc00c
-#define MDFLD_PWRGT_DISPLAY_STS_B0 (MDFLD_PWRGT_DISPLAY_A_STS_B0 |
MDFLD_PWRGT_DISPLAY_C_STS_B0)// 0x000fc00c
+#define MDFLD_PWRGT_DISPLAY_STS_A0 (MDFLD_PWRGT_DISPLAY_A_STS |
MDFLD_PWRGT_DISPLAY_B_STS | MDFLD_PWRGT_DISPLAY_C_STS |
MDFLD_PWRGT_DISP_MIPI_STS)// 0x000fc00c
+#define MDFLD_PWRGT_DISPLAY_STS_B0 (MDFLD_PWRGT_DISPLAY_A_STS_B0 |
MDFLD_PWRGT_DISPLAY_B_STS_B0 | MDFLD_PWRGT_DISPLAY_C_STS_B0 |
MDFLD_PWRGT_DISP_MIPI_STS)// 0x000fc00c
#endif
diff --git a/drivers/staging/mrst/pvr/services4/system/unified/sysconfig.c
b/drivers/staging/mrst/pvr/services4/system/unified/sysconfig.c
index 1053174..abadea2 100644
--- a/drivers/staging/mrst/pvr/services4/system/unified/sysconfig.c
+++ b/drivers/staging/mrst/pvr/services4/system/unified/sysconfig.c
@@ -1163,9 +1163,9 @@ PVRSRV_ERROR SysDevicePrePowerState(IMG_UINT32
ui32DeviceIndex,
{
PVR_DPF((PVR_DBG_MESSAGE,"SysDevicePrePowerState:
Remove SGX power"));
#if defined(SUPPORT_DRI_DRM_EXT)
- ospm_power_using_hw_end(OSPM_GRAPHICS_ISLAND);
psb_irq_uninstall_islands(gpDrmDevice,
OSPM_GRAPHICS_ISLAND);
ospm_power_island_down(OSPM_GRAPHICS_ISLAND);
+ ospm_power_using_hw_end(OSPM_GRAPHICS_ISLAND);
#endif
}
#if 0
--
1.7.1
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