> On your question of using SRAM for all of system RAM, from what little I
> know, I'd guess it would draw a lot of power, but it could work. I don't
> know
> if any of the motherboard chipsets are set up to drive SRAM as main
> memory, so that might be a hurdle you'd have to get over.
they aren't. It would require a completely custom host bus controller. On
the standard chipsets, this is integrated along with the host-to-PCI bridge,
so your custom controller would have to duplicate this functionality too.
And, its unclear how much gain this might have over SDRAM. Typical 100Mhz bus
operation on pentium-II 350MHz and up is like 5-1-1-1-1-1-1-1 clocks for a 8
cycle by 8 byte burst, or 14 clocks total per 64 bytes. Now, far as I know,
the fastest the pentium-II bus can go is 2-1-1-1-1-1-1-1 or 9 clocks per 64
bytes. To achieve this, the static ram would have to have cycle times well
under 10nS and be implemented in a fully synchronous design (one bus driver's
worth of delay here could account for 5nS or more out of the 10nS available
cycle!). And, this 14->9 speedup will only occur on level-2 cache miss cycles
and write cycles.
To achieve the 8 byte wide bus, you'd probably use 8 1Mx8 SRAMs for a total of
8MBytes. Hmm. 8Mbit density SRAMs appear to come in 256K x 32bit, so we'd
instead need 4 banks of them which would greatly complicate the design. These
parts come in speeds from 5nS to 10nS so they are fast enough. They are
synchronous burst SRAM's so at least they would simplify the design by
eliminating external address counters. Power supply currents are from 250 to
500mA at 3.3V per chip, so our design will require 8 of these or 2 to 4 amps
total, 7 to 15 watts. It appears in a carefully controlled synchronous
design, they are capable of address->data in 2 clocks, then up to 3 more
cycles at one clock each, this looks like we'll have to interleave two banks
to achieve the peak 2-1-1-1-1-1-1-1 timing using the 10nS (100MHz) parts...
Worse, it appears that 8Mbit 100MHz+ synchronous SRAM is just entering
production. These parts are gonna be $$$$$, so we might have to build it from
8 banks of 2 each 128kx32 SRAMs (which are 4Mbit each).
Nope, I don't see this as practical at all.
-jrp
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