> But some new instructions of the PIII can probably improve a
> little bit the
> programs: the prefetch instructions. We can control prefetch and
> then fetch
> data into all cache levels before using them. The bottleneck of memory I/O
> can now be controlled easily ...
I looked at the instructions too and didn't see anything really useful.
But yes, the code could be optimized a bit in it's use of memory, and
perhaps gain a small percentage improvement.
If I'm not mistaken, doesn't Prime95 already have different routines to take
advantage of the processor being run on? I suppose George could get really
carried away, like trying to minimize potential cache-hits on cacheless
Celeron chips, but that may be a bit much.
Does the new AMD chip coming out offer any new instructions that would be of
use? And as for the Merced, it's an almost entire redesign of the Pentium
line, where the program will now be responsible for optimizing use of
pipelined instructions, or speculative execution. But the execution of the
instructions themselves are probably about the same. I have heard that FP
speeds would go up some though... Prime95 may run slower on a Merced at the
same clock speed as a Xeon, at least until it's recompiled. Sigh...
At least by the time Merced comes out, the 0.18 fabs will be busy cranking
out chips and we can see Merceds running 750MHz, or whatever, to start.
I can't reveal my source, but someone at Intel did mention "copper" to me,
so perhaps they'll start really moving that way, promising even greater
speeds.
What Intel needs to do is some redesign of FP speeds to catch up with RISC
design. As it is, they've been holding their own by increasing clock speeds
to new highs, but that'll only get you so much.
________________________________________________________________
Unsubscribe & list info -- http://www.scruz.net/~luke/signup.htm
