At 09:35 PM 11/4/2001 +0000, [EMAIL PROTECTED] wrote: >I'm not sure I fully understand the way in which a SMT processor >would utilise cache.
This is a prime95 problem, not a SMT problem. Prime95 is designed to run efficiently in 128KB of L2 cache. If I split the current FFT into 2 threads, then either each thread is going to want 128KB of L2 cache space (more cache contention) or I must recode the "passes" of prime95 to run efficiently in just 64KB of cache (this might be a bad idea as using less L2 cache may require adding another "pass" over the FFT data - at least for some FFT sizes). That is why I fear that SMT may not be helpful to prime95. Another way of saying this is prime95 may be more constrained by L2 cache sizes than it constrained by micro-op scheduling. However, I had not considered the idea of factoring and LL testing. Even better, if we make the factoring code use mostly integer instructions then the LL test thread would keep the FPU units busy and the factoring thread would keep the integer units busy! Then the only question becomes "Does the user want to slow down his LL tests in order to increase his total (LL + factoring) throughput". -- George _________________________________________________________________________ Unsubscribe & list info -- http://www.scruz.net/~luke/signup.htm Mersenne Prime FAQ -- http://www.tasam.com/~lrwiman/FAQ-mers
