George Woltman wrote: > This is a prime95 problem, not a SMT problem. Prime95 is designed to > run efficiently in 128KB of L2 cache.
George- Are there any gains to be had if you code it to fit a 256KB L2? If so, maybe we should have 2 versions? :) Also, how do you think the new .13 micron Tualatin CPUs will do for Prime95? I read someting about a new pre-fetch mechanism (?) but I didn't quite grasp what it meant... The newer PIIIs (1.13 & 1.26GHZ, IIRC...) have an option for 512KB... Thanks! Xyzzy [81/117.943/94/9.801/801.750] http://www.teamprimerib.com/ _________________________________________________________________________ Unsubscribe & list info -- http://www.scruz.net/~luke/signup.htm Mersenne Prime FAQ -- http://www.tasam.com/~lrwiman/FAQ-mers
