George Woltman wrote: > I agree with Steinar's intriguing observation. Intel's SMT looks > like two CPUs to the operating system but the two CPUs share > one core.
Oh no, they're not going to cobble something together like that are they? This looks like another forthcoming disaster where the chance to make a real technological leap is squandered in the name of "compatibility" with some OS that firstly didn't deserve such an effort, and secondly could have been patched anyway. I hope they leave a mechanism for proper OSs to take full control and assign the parallel threads themselves, otherwise this will be another PC architectural compromise that blights performance or otherwise adds timewasting complexity like say: register sharing for MMX and FPU, cascaded IRQs, FPU IRQ, polled gameport, the whole of real mode(!), shite DMA, that "pretend the boot CD is actually a floppy disk" crap, and many others. The idea of SMT is to be able to feed all execution pipelines simultaneously, by allowing instructions to be drawn from several threads. So for example, when an application has nothing but integer instructions to execute, then floating-point instructions can be drawn from a process waiting to execute these and fed down the then idle floating point pipelines. For computational applications this is significantly different from having two processors. Prime95/mprime should be saved by accident rather than design - It executes mostly floating point, so will not compete head-on with "ordinary" apps which are mostly or entirely integer. The following article explained SMT (on the proposed Alpha EV8) for me: http://www.realworldtech.com/page.cfm?ArticleID=RWT122600000000 Yours, ======= Gareth Randall ======= _________________________________________________________________________ Unsubscribe & list info -- http://www.ndatech.com/mersenne/signup.htm Mersenne Prime FAQ -- http://www.tasam.com/~lrwiman/FAQ-mers
