Module: Mesa Branch: main Commit: 031bbdfbe681ac45d2c19aa7813d863599fda785 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=031bbdfbe681ac45d2c19aa7813d863599fda785
Author: Samuel Pitoiset <[email protected]> Date: Thu Feb 2 10:12:51 2023 +0100 radv: stop using the graphics pipeline key after compilation Only the blend state was relying on the graphics pipeline key. This will allow us to skip generating it when there is no compilation at all (for fast-linking with GPL). Signed-off-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21068> --- src/amd/vulkan/radv_pipeline.c | 42 ++++++++++++++++++++++++--------------- src/amd/vulkan/radv_shader.h | 2 ++ src/amd/vulkan/radv_shader_info.c | 4 ++++ 3 files changed, 32 insertions(+), 16 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index c0f90468d81..4ce14a3fd3b 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -449,15 +449,35 @@ radv_can_enable_dual_src(const struct vk_color_blend_attachment_state *att) return false; } +static bool +radv_pipeline_needs_dynamic_ps_epilog(const struct radv_graphics_pipeline *pipeline) +{ + /* These dynamic states need to compile PS epilogs on-demand. */ + return !!(pipeline->dynamic_states & (RADV_DYNAMIC_COLOR_BLEND_ENABLE | + RADV_DYNAMIC_COLOR_WRITE_MASK | + RADV_DYNAMIC_ALPHA_TO_COVERAGE_ENABLE | + RADV_DYNAMIC_COLOR_BLEND_EQUATION)); +} + static struct radv_blend_state radv_pipeline_init_blend_state(struct radv_graphics_pipeline *pipeline, - const struct vk_graphics_pipeline_state *state, - const struct radv_pipeline_key *key) + const struct vk_graphics_pipeline_state *state) { + const struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT]; struct radv_blend_state blend = {0}; + unsigned spi_shader_col_format = 0; - blend.cb_shader_mask = ac_get_cb_shader_mask(key->ps.epilog.spi_shader_col_format); - blend.spi_shader_col_format = key->ps.epilog.spi_shader_col_format; + if (radv_pipeline_needs_dynamic_ps_epilog(pipeline)) + return blend; + + if (ps->info.ps.has_epilog) { + spi_shader_col_format = pipeline->ps_epilog->spi_shader_col_format; + } else { + spi_shader_col_format = ps->info.ps.spi_shader_col_format; + } + + blend.cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format); + blend.spi_shader_col_format = spi_shader_col_format; return blend; } @@ -2114,16 +2134,6 @@ radv_graphics_pipeline_link(const struct radv_graphics_pipeline *pipeline, } } -static bool -radv_pipeline_needs_dynamic_ps_epilog(const struct radv_graphics_pipeline *pipeline) -{ - /* These dynamic states need to compile PS epilogs on-demand. */ - return !!(pipeline->dynamic_states & (RADV_DYNAMIC_COLOR_BLEND_ENABLE | - RADV_DYNAMIC_COLOR_WRITE_MASK | - RADV_DYNAMIC_ALPHA_TO_COVERAGE_ENABLE | - RADV_DYNAMIC_COLOR_BLEND_EQUATION)); -} - struct radv_pipeline_key radv_generate_pipeline_key(const struct radv_pipeline *pipeline, VkPipelineCreateFlags flags) { @@ -5003,13 +5013,13 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv if (device->physical_device->rad_info.gfx_level >= GFX10_3) gfx103_pipeline_init_vrs_state(pipeline, &state); - struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, &state, &key); + struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, &state); /* Copy the non-compacted SPI_SHADER_COL_FORMAT which is used to emit RBPLUS state. */ pipeline->col_format_non_compacted = blend.spi_shader_col_format; struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT]; - bool enable_mrt_compaction = !key.ps.epilog.mrt0_is_dual_src && !ps->info.ps.has_epilog; + bool enable_mrt_compaction = !ps->info.ps.has_epilog && !ps->info.ps.mrt0_is_dual_src; if (enable_mrt_compaction) { blend.spi_shader_col_format = radv_compact_spi_shader_col_format(ps, &blend); diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 7d2a2a6bebb..3069b69159f 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -342,8 +342,10 @@ struct radv_shader_info { uint8_t depth_layout; bool allow_flat_shading; bool has_epilog; + bool mrt0_is_dual_src; unsigned spi_ps_input; unsigned colors_written; + unsigned spi_shader_col_format; uint8_t color0_written; } ps; struct { diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index 3e25671552b..c04711673e0 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -578,6 +578,10 @@ gather_shader_info_fs(const nir_shader *nir, const struct radv_pipeline_key *pip (pipeline_key->ps.alpha_to_coverage_via_mrtz && (info->ps.color0_written & 0x8)) && (info->ps.writes_z || info->ps.writes_stencil || info->ps.writes_sample_mask); + info->ps.mrt0_is_dual_src = pipeline_key->ps.epilog.mrt0_is_dual_src; + + info->ps.spi_shader_col_format = pipeline_key->ps.epilog.spi_shader_col_format; + nir_foreach_shader_in_variable(var, nir) { unsigned attrib_count = glsl_count_attribute_slots(var->type, false); int idx = var->data.location;
