Module: Mesa Branch: main Commit: 8cd8d6bcccea8fb66d7fa2c368833ebda362e3b2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8cd8d6bcccea8fb66d7fa2c368833ebda362e3b2
Author: Francisco Jerez <[email protected]> Date: Thu Jun 30 15:46:48 2022 -0700 intel: Add debug flags for enabling Xe2+ multipolygon fragment shader dispatch modes. Note that the multipolygon PS disptach modes supported by Xe2 aren't enabled by default yet, but they can be enabled manually via INTEL_SIMD_DEBUG=fs2x8,fs4x8,fs2x16. Reviewed-by: Caio Oliveira <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26606> --- src/intel/dev/intel_debug.c | 2 ++ src/intel/dev/intel_debug.h | 28 +++++++++++++++------------- 2 files changed, 17 insertions(+), 13 deletions(-) diff --git a/src/intel/dev/intel_debug.c b/src/intel/dev/intel_debug.c index acf5d2cde51..765b7e6f782 100644 --- a/src/intel/dev/intel_debug.c +++ b/src/intel/dev/intel_debug.c @@ -116,6 +116,8 @@ static const struct debug_control simd_control[] = { { "fs16", DEBUG_FS_SIMD16 }, { "fs32", DEBUG_FS_SIMD32 }, { "fs2x8", DEBUG_FS_SIMD2X8 }, + { "fs4x8", DEBUG_FS_SIMD4X8 }, + { "fs2x16", DEBUG_FS_SIMD2X16 }, { "cs8", DEBUG_CS_SIMD8 }, { "cs16", DEBUG_CS_SIMD16 }, { "cs32", DEBUG_CS_SIMD32 }, diff --git a/src/intel/dev/intel_debug.h b/src/intel/dev/intel_debug.h index 9a48b5a99c7..75ec2ad81fa 100644 --- a/src/intel/dev/intel_debug.h +++ b/src/intel/dev/intel_debug.h @@ -118,24 +118,26 @@ extern uint32_t intel_debug_bkp_after_draw_count; #define DEBUG_FS_SIMD16 (1ull << 1) #define DEBUG_FS_SIMD32 (1ull << 2) #define DEBUG_FS_SIMD2X8 (1ull << 3) +#define DEBUG_FS_SIMD4X8 (1ull << 4) +#define DEBUG_FS_SIMD2X16 (1ull << 5) -#define DEBUG_CS_SIMD8 (1ull << 4) -#define DEBUG_CS_SIMD16 (1ull << 5) -#define DEBUG_CS_SIMD32 (1ull << 6) +#define DEBUG_CS_SIMD8 (1ull << 6) +#define DEBUG_CS_SIMD16 (1ull << 7) +#define DEBUG_CS_SIMD32 (1ull << 8) -#define DEBUG_TS_SIMD8 (1ull << 7) -#define DEBUG_TS_SIMD16 (1ull << 8) -#define DEBUG_TS_SIMD32 (1ull << 9) +#define DEBUG_TS_SIMD8 (1ull << 9) +#define DEBUG_TS_SIMD16 (1ull << 10) +#define DEBUG_TS_SIMD32 (1ull << 11) -#define DEBUG_MS_SIMD8 (1ull << 10) -#define DEBUG_MS_SIMD16 (1ull << 11) -#define DEBUG_MS_SIMD32 (1ull << 12) +#define DEBUG_MS_SIMD8 (1ull << 12) +#define DEBUG_MS_SIMD16 (1ull << 13) +#define DEBUG_MS_SIMD32 (1ull << 14) -#define DEBUG_RT_SIMD8 (1ull << 13) -#define DEBUG_RT_SIMD16 (1ull << 14) -#define DEBUG_RT_SIMD32 (1ull << 15) +#define DEBUG_RT_SIMD8 (1ull << 15) +#define DEBUG_RT_SIMD16 (1ull << 16) +#define DEBUG_RT_SIMD32 (1ull << 17) -#define SIMD_DISK_CACHE_MASK ((1ull << 16) - 1) +#define SIMD_DISK_CACHE_MASK ((1ull << 18) - 1) #ifdef HAVE_ANDROID_PLATFORM #define LOG_TAG "INTEL-MESA"
