Module: Mesa Branch: main Commit: ef6ef7aa8eb71cbaff0de401f18df0836f005607 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef6ef7aa8eb71cbaff0de401f18df0836f005607
Author: Francisco Jerez <[email protected]> Date: Sat Jun 11 17:35:27 2022 -0700 intel/fs/xe2+: Implement PS thread payload register offset setup. The PS thread payload format has changed enough in Xe2 that it probably doesn't make sense to share code with gfx6. See BSpec page "PS Thread Payload for Normal Dispatch - 512 bit GRF" for the new format. Reviewed-by: Caio Oliveira <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26606> --- src/intel/compiler/brw_fs_thread_payload.cpp | 80 +++++++++++++++++++++++++++- 1 file changed, 78 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_fs_thread_payload.cpp b/src/intel/compiler/brw_fs_thread_payload.cpp index 79e4eba53be..1ad4f38d8c8 100644 --- a/src/intel/compiler/brw_fs_thread_payload.cpp +++ b/src/intel/compiler/brw_fs_thread_payload.cpp @@ -150,6 +150,80 @@ gs_thread_payload::gs_thread_payload(fs_visitor &v) } } +static inline void +setup_fs_payload_gfx20(fs_thread_payload &payload, + const fs_visitor &v, + bool &source_depth_to_render_target) +{ + struct brw_wm_prog_data *prog_data = brw_wm_prog_data(v.prog_data); + const unsigned payload_width = 16; + assert(v.dispatch_width % payload_width == 0); + assert(v.devinfo->ver >= 20); + + for (unsigned j = 0; j < v.dispatch_width / payload_width; j++) { + /* R0-1: PS thread payload header, masks and pixel X/Y coordinates. */ + payload.num_regs++; + payload.subspan_coord_reg[j] = payload.num_regs++; + } + + for (unsigned j = 0; j < v.dispatch_width / payload_width; j++) { + /* R2-13: Barycentric interpolation coordinates. These appear + * in the same order that they appear in the brw_barycentric_mode + * enum. Each set of coordinates occupies 2 64B registers per + * SIMD16 half. Coordinates only appear if they were enabled + * using the "Barycentric Interpolation Mode" bits in WM_STATE. + */ + for (int i = 0; i < BRW_BARYCENTRIC_MODE_COUNT; ++i) { + if (prog_data->barycentric_interp_modes & (1 << i)) { + payload.barycentric_coord_reg[i][j] = payload.num_regs; + payload.num_regs += payload_width / 4; + } + } + + /* R14: Interpolated depth if "Pixel Shader Uses Source Depth" is set. */ + if (prog_data->uses_src_depth) { + payload.source_depth_reg[j] = payload.num_regs; + payload.num_regs += payload_width / 8; + } + + /* R15: Interpolated W if "Pixel Shader Uses Source W" is set. */ + if (prog_data->uses_src_w) { + payload.source_w_reg[j] = payload.num_regs; + payload.num_regs += payload_width / 8; + } + + /* R16: MSAA input coverage mask if "Pixel Shader Uses Input + * Coverage Mask" is set. + */ + if (prog_data->uses_sample_mask) { + payload.sample_mask_in_reg[j] = payload.num_regs; + payload.num_regs += payload_width / 8; + } + + /* R19: MSAA position XY offsets if "Position XY Offset Select" + * is either POSOFFSET_CENTROID or POSOFFSET_SAMPLE. Note that + * this is delivered as a single SIMD32 vector, inconsistently + * with most other PS payload fields. + */ + if (prog_data->uses_pos_offset && j == 0) { + for (unsigned k = 0; k < 2; k++) { + payload.sample_pos_reg[k] = payload.num_regs; + payload.num_regs++; + } + } + } + + if (prog_data->uses_depth_w_coefficients) { + assert(v.max_polygons == 1); + payload.depth_w_coef_reg = payload.num_regs; + payload.num_regs += 2; + } + + if (v.nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) { + source_depth_to_render_target = true; + } +} + static inline void setup_fs_payload_gfx6(fs_thread_payload &payload, const fs_visitor &v, @@ -159,7 +233,7 @@ setup_fs_payload_gfx6(fs_thread_payload &payload, const unsigned payload_width = MIN2(16, v.dispatch_width); assert(v.dispatch_width % payload_width == 0); - assert(v.devinfo->ver >= 6); + assert(v.devinfo->ver >= 6 && v.devinfo->ver < 20); payload.num_regs = 0; @@ -381,7 +455,9 @@ fs_thread_payload::fs_thread_payload(const fs_visitor &v, depth_w_coef_reg(), barycentric_coord_reg() { - if (v.devinfo->ver >= 6) + if (v.devinfo->ver >= 20) + setup_fs_payload_gfx20(*this, v, source_depth_to_render_target); + else if (v.devinfo->ver >= 6) setup_fs_payload_gfx6(*this, v, source_depth_to_render_target); else setup_fs_payload_gfx4(*this, v, source_depth_to_render_target,
