Mesa (main): intel/xe2+: Implement fragment shader dispatch state setup.

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Module: Mesa
Branch: main
Commit: d8ad51ec76c1d84747b1c74d93405ae73645d19d
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8ad51ec76c1d84747b1c74d93405ae73645d19d

Author: Francisco Jerez <curroje...@riseup.net>
Date:   Thu Nov 30 23:04:06 2023 -0800

intel/xe2+: Implement fragment shader dispatch state setup.

This sets up the PS dispatch controls to a supported combination of
Kernel0/Kernel1 dispatch modes, initializing the polygon packing
controls to use a multipolygon dispatch mode if one was provided.

Rework:
 * Jordan: Move into intel_update_ps_state()

Reviewed-by: Caio Oliveira <caio.olive...@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26606>

---

 src/intel/common/intel_genX_state.h | 41 ++++++++++++++++++++++++++++++-------
 1 file changed, 34 insertions(+), 7 deletions(-)

diff --git a/src/intel/common/intel_genX_state.h 
b/src/intel/common/intel_genX_state.h
index 919a6d10b86..affd82de277 100644
--- a/src/intel/common/intel_genX_state.h
+++ b/src/intel/common/intel_genX_state.h
@@ -118,16 +118,43 @@ intel_set_ps_dispatch_state(struct GENX(3DSTATE_PS) *ps,
    }
 
    assert(enable_8 || enable_16 || enable_32 ||
-          (GFX_VER == 12 && prog_data->dispatch_multi));
+          (GFX_VER >= 12 && prog_data->dispatch_multi));
    assert(!prog_data->dispatch_multi ||
-          (GFX_VER == 12 && !enable_8));
+          (GFX_VER >= 12 && !enable_8));
 
 #if GFX_VER >= 20
-   assert(!enable_8);
-   ps->Kernel0Enable = enable_16 || enable_32;
-   ps->Kernel0SIMDWidth = enable_16 ? 0 : 1;
-   ps->Kernel1Enable = enable_16 && enable_32;
-   ps->Kernel1SIMDWidth = SIMD32 /* SIMD32 */;
+   if (prog_data->dispatch_multi) {
+      ps->Kernel0Enable = true;
+      ps->Kernel0SIMDWidth = (prog_data->dispatch_multi == 32 ?
+                              PS_SIMD32 : PS_SIMD16);
+      ps->Kernel0MaximumPolysperThread =
+         prog_data->max_polygons - 1;
+      switch (prog_data->dispatch_multi /
+              prog_data->max_polygons) {
+      case 8:
+         ps->Kernel0PolyPackingPolicy = POLY_PACK8_FIXED;
+         break;
+      case 16:
+         ps->Kernel0PolyPackingPolicy = POLY_PACK16_FIXED;
+         break;
+      default:
+         unreachable("Invalid polygon width");
+      }
+
+   } else if (enable_16) {
+      ps->Kernel0Enable = true;
+      ps->Kernel0SIMDWidth = PS_SIMD16;
+      ps->Kernel0PolyPackingPolicy = POLY_PACK16_FIXED;
+   }
+
+   if (enable_32) {
+      ps->Kernel1Enable = true;
+      ps->Kernel1SIMDWidth = PS_SIMD32;
+
+   } else if (enable_16 && prog_data->dispatch_multi == 16) {
+      ps->Kernel1Enable = true;
+      ps->Kernel1SIMDWidth = PS_SIMD16;
+   }
 #else
    ps->_8PixelDispatchEnable = enable_8 ||
       (GFX_VER == 12 && prog_data->dispatch_multi);