We're about to call this function in a bunch of state emits, so let's not spam the hardware with flushes too hard. --- src/mesa/drivers/dri/i965/brw_draw.c | 2 ++ src/mesa/drivers/dri/i965/brw_vtbl.c | 5 +++++ src/mesa/drivers/dri/intel/intel_batchbuffer.c | 5 +++++ src/mesa/drivers/dri/intel/intel_context.h | 2 ++ 4 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 6144f0a..350fc51 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -177,6 +177,8 @@ static void brw_emit_prim(struct brw_context *brw, OUT_BATCH(base_vertex_location); ADVANCE_BATCH(); + intel->batch.need_workaround_flush = true; + if (intel->always_flush_cache) { intel_batchbuffer_emit_mi_flush(intel); } diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c index 236c4d2..ed4c9c6 100644 --- a/src/mesa/drivers/dri/i965/brw_vtbl.c +++ b/src/mesa/drivers/dri/i965/brw_vtbl.c @@ -124,6 +124,11 @@ static void brw_new_batch( struct intel_context *intel ) */ brw->state.dirty.brw |= BRW_NEW_CONTEXT | BRW_NEW_BATCH; + /* Assume that the last command before the start of our batch was a + * primitive, for safety. + */ + intel->batch.need_workaround_flush = true; + brw->vb.nr_current_buffers = 0; } diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c index 9e8f8b5..77563ae 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c @@ -296,6 +296,9 @@ emit: static void intel_emit_post_sync_nonzero_flush(struct intel_context *intel) { + if (!intel->batch.need_workaround_flush) + return; + BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_PIPE_CONTROL); OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE); @@ -303,6 +306,8 @@ intel_emit_post_sync_nonzero_flush(struct intel_context *intel) I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT, 0); OUT_BATCH(0); /* write data */ ADVANCE_BATCH(); + + intel->batch.need_workaround_flush = false; } /* Emit a pipelined flush to either flush render and texture cache for diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index 751af45..148fb0c 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -183,6 +183,8 @@ struct intel_context drm_intel_bo *last_bo; /** BO for post-sync nonzero writes for gen6 workaround. */ drm_intel_bo *workaround_bo; + bool need_workaround_flush; + struct cached_batch_item *cached_items; uint16_t emit, total; -- 1.7.5.3 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev