This surface state control has been supported by all hardware
generations since G45.
---
src/mesa/drivers/dri/i965/brw_device_info.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c
b/src/mesa/drivers/dri/i965/brw_device_info.c
index 77bbe78..4d90aa3 100644
--- a/src/mesa/drivers/dri/i965/brw_device_info.c
+++ b/src/mesa/drivers/dri/i965/brw_device_info.c
@@ -252,6 +252,7 @@ static const struct brw_device_info brw_device_info_hsw_gt3
= {
.has_llc = true, \
.has_pln = true, \
.supports_simd16_3src = true, \
+ .has_surface_tile_offset = true, \
.max_vs_threads = 504, \
.max_hs_threads = 504, \
.max_ds_threads = 504, \
@@ -332,6 +333,7 @@ static const struct brw_device_info brw_device_info_chv = {
.has_llc = true, \
.has_pln = true, \
.supports_simd16_3src = true, \
+ .has_surface_tile_offset = true, \
.max_vs_threads = 336, \
.max_gs_threads = 336, \
.max_hs_threads = 336, \
--
2.9.0
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