From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_state_draw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 8508259..ec564c1 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -986,20 +986,21 @@ void si_emit_cache_flush(struct si_context *sctx)
/* Ideally flush TC together with CB/DB. */
if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2) {
tc_flags |= EVENT_TC_ACTION_ENA |
EVENT_TCL1_ACTION_ENA;
/* Clear the flags. */
rctx->flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 |
SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
SI_CONTEXT_INV_VMEM_L1);
+ sctx->b.num_L2_invalidates++;
}
/* Allocate memory for the fence. */
u_suballocator_alloc(rctx->allocator_zeroed_memory, 4, 4,
&offset, (struct pipe_resource**)&rbuf);
va = rbuf->gpu_address + offset;
r600_gfx_write_event_eop(rctx, cb_db_event, tc_flags, 1,
rbuf, va, 0, 1);
r600_gfx_wait_fence(rctx, va, 1, 0xffffffff);
--
2.7.4
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