From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_clear.c | 23 ++++++++++-------------
src/gallium/drivers/radeonsi/si_texture.c | 6 +++++-
2 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_clear.c
b/src/gallium/drivers/radeonsi/si_clear.c
index 0e2d2f1013b..ef843966f2a 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -438,33 +438,30 @@ static void si_do_fast_color_clear(struct si_context
*sctx,
continue;
if (sctx->chip_class <= VI &&
tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D
&&
!sctx->screen->info.htile_cmask_support_1d_tiling)
continue;
/* Fast clear is the most appropriate place to enable DCC for
* displayable surfaces.
*/
- if (sctx->chip_class >= VI &&
- !(sctx->screen->debug_flags & DBG(NO_DCC_FB))) {
- vi_separate_dcc_try_enable(sctx, tex);
-
- /* RB+ isn't supported with a CMASK clear only on
Stoney,
- * so all clears are considered to be hypothetically
slow
- * clears, which is weighed when determining whether to
- * enable separate DCC.
- */
- if (tex->dcc_gather_statistics &&
- sctx->family == CHIP_STONEY)
- tex->num_slow_clears++;
- }
+ vi_separate_dcc_try_enable(sctx, tex);
+
+ /* RB+ isn't supported with a CMASK clear only on Stoney,
+ * so all clears are considered to be hypothetically slow
+ * clears, which is weighed when determining whether to
+ * enable separate DCC.
+ */
+ if (tex->dcc_gather_statistics &&
+ sctx->family == CHIP_STONEY)
+ tex->num_slow_clears++;
bool need_decompress_pass = false;
/* Use a slow clear for small surfaces where the cost of
* the eliminate pass can be higher than the benefit of fast
* clear. The closed driver does this, but the numbers may
differ.
*
* This helps on both dGPUs and APUs, even small APUs like
Mullins.
*/
bool too_small = tex->buffer.b.b.nr_samples <= 1 &&
diff --git a/src/gallium/drivers/radeonsi/si_texture.c
b/src/gallium/drivers/radeonsi/si_texture.c
index e1afe71a3c7..75479dcddff 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -2230,23 +2230,27 @@ static bool vi_should_enable_separate_dcc(struct
r600_texture *tex)
void vi_separate_dcc_try_enable(struct si_context *sctx,
struct r600_texture *tex)
{
/* The intent is to use this with shared displayable back buffers,
* but it's not strictly limited only to them.
*/
if (!tex->buffer.b.is_shared ||
!(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) ||
tex->buffer.b.b.target != PIPE_TEXTURE_2D ||
tex->buffer.b.b.last_level > 0 ||
- !tex->surface.dcc_size)
+ !tex->surface.dcc_size ||
+ sctx->screen->debug_flags & DBG(NO_DCC) ||
+ sctx->screen->debug_flags & DBG(NO_DCC_FB))
return;
+ assert(sctx->chip_class >= VI);
+
if (tex->dcc_offset)
return; /* already enabled */
/* Enable the DCC stat gathering. */
if (!tex->dcc_gather_statistics) {
tex->dcc_gather_statistics = true;
vi_separate_dcc_start_query(sctx, tex);
}
if (!vi_should_enable_separate_dcc(tex))
--
2.17.1
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
