On Fri, 2018-12-07 at 11:57 -0600, Jason Ekstrand wrote: > On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga <ito...@igalia.com> > wrote: > > From the Skylake PRM, Extended Math Function: > > > > > > > > "The execution size must be no more than 8 when half-floats > > > > are used in source or destination operand." > > > > > > > > Earlier generations do not support Extended Math with half-float. > > > > --- > > > > src/intel/compiler/brw_fs.cpp | 30 +++++++++++++++++++++++------- > > > > 1 file changed, 23 insertions(+), 7 deletions(-) > > > > > > > > diff --git a/src/intel/compiler/brw_fs.cpp > > b/src/intel/compiler/brw_fs.cpp > > > > index 43b920ae33d..509c6febf38 100644 > > > > --- a/src/intel/compiler/brw_fs.cpp > > > > +++ b/src/intel/compiler/brw_fs.cpp > > > > @@ -5386,18 +5386,34 @@ get_lowered_simd_width(const struct > > gen_device_info *devinfo, > > > > case SHADER_OPCODE_EXP2: > > > > case SHADER_OPCODE_LOG2: > > > > case SHADER_OPCODE_SIN: > > > > - case SHADER_OPCODE_COS: > > > > + case SHADER_OPCODE_COS: { > > > > /* Unary extended math instructions are limited to SIMD8 on > > Gen4 and > > > > * Gen6. > > > > */ > > > > - return (devinfo->gen >= 7 ? MIN2(16, inst->exec_size) : > > > > - devinfo->gen == 5 || devinfo->is_g4x ? MIN2(16, > > inst->exec_size) : > > > > - MIN2(8, inst->exec_size)); > > > > + unsigned max_width = > > > > + (devinfo->gen >= 7 ? MIN2(16, inst->exec_size) : > > > > + devinfo->gen == 5 || devinfo->is_g4x ? MIN2(16, inst- > > >exec_size) : > > > > + MIN2(8, inst->exec_size)); > > Curro went a lot of work to structure this as a nested ternary. I > agree that that isn't really holding up anymore but if we're going to > break with it, let's break with it in a more readable way: > > if (devinfo->gen == 6 || (devinfo->gen == 4 && !devinfo->is_g4x)) > return MIN2(8, inst->exec_size); > if (inst->dst.type == BRW_REGISTER_TYPE_HF) > return MIN2(8, inst->exec_size); > else > return MIN2(16, inst->exec_size);
Sure, will do that. > > - case SHADER_OPCODE_POW: > > > > + /* Extended Math Function is limited to SIMD8 with half- > > float */ > > > > + if (inst->dst.type == BRW_REGISTER_TYPE_HF) > > > > + max_width = MIN2(max_width, 8); > > > > + > > > > + return max_width; > > > > + } > > > > + > > > > + case SHADER_OPCODE_POW: { > > > > /* SIMD16 is only allowed on Gen7+. */ > > > > - return (devinfo->gen >= 7 ? MIN2(16, inst->exec_size) : > > > > - MIN2(8, inst->exec_size)); > > > > + unsigned max_width = > > > > + (devinfo->gen >= 7 ? MIN2(16, inst->exec_size) : > > > > + MIN2(8, inst->exec_size)); > > > > + > > > > + /* Extended Math Function is limited to SIMD8 with half- > > float */ > > > > + if (inst->dst.type == BRW_REGISTER_TYPE_HF) > > > > + max_width = MIN2(max_width, 8); > > > > + > > > > + return max_width; > > > > + } > > > > > > > > case SHADER_OPCODE_INT_QUOTIENT: > > > > case SHADER_OPCODE_INT_REMAINDER: > >
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