--- src/intel/vulkan/anv_genX.h | 4 ++ src/intel/vulkan/genX_pipeline.c | 40 +-------------- src/intel/vulkan/genX_state.c | 84 ++++++++++++++++++++++++-------- 3 files changed, 70 insertions(+), 58 deletions(-)
diff --git a/src/intel/vulkan/anv_genX.h b/src/intel/vulkan/anv_genX.h index 8fd32cabf1e..55226179124 100644 --- a/src/intel/vulkan/anv_genX.h +++ b/src/intel/vulkan/anv_genX.h @@ -74,6 +74,10 @@ genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch, VkShaderStageFlags active_stages, const unsigned entry_size[4]); +void genX(emit_multisample)(struct anv_batch *batch, uint32_t samples); + +void genX(emit_sample_pattern)(struct anv_batch *batch); + void genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, struct anv_address dst, struct anv_address src, uint32_t size); diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index 8ba206ed8c4..7eb05333dad 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -551,45 +551,9 @@ static void emit_ms_state(struct anv_pipeline *pipeline, const VkPipelineMultisampleStateCreateInfo *info) { - uint32_t samples = 1; - uint32_t log2_samples = 0; + uint32_t samples = info ? info->rasterizationSamples : 1; - if (info) { - samples = info->rasterizationSamples; - log2_samples = __builtin_ffs(samples) - 1; - } - - anv_batch_emit(&pipeline->batch, GENX(3DSTATE_MULTISAMPLE), ms) { - ms.NumberofMultisamples = log2_samples; - - ms.PixelLocation = CENTER; -#if GEN_GEN >= 8 - /* The PRM says that this bit is valid only for DX9: - * - * SW can choose to set this bit only for DX9 API. DX10/OGL API's - * should not have any effect by setting or not setting this bit. - */ - ms.PixelPositionOffsetEnable = false; -#else - - switch (samples) { - case 1: - GEN_SAMPLE_POS_1X(ms.Sample); - break; - case 2: - GEN_SAMPLE_POS_2X(ms.Sample); - break; - case 4: - GEN_SAMPLE_POS_4X(ms.Sample); - break; - case 8: - GEN_SAMPLE_POS_8X(ms.Sample); - break; - default: - break; - } -#endif - } + genX(emit_multisample)(&pipeline->batch, samples); anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SAMPLE_MASK), sm) { /* From the Vulkan 1.0 spec: diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index cffd1e47247..cc066e68f2c 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -139,22 +139,7 @@ genX(init_device_state)(struct anv_device *device) #if GEN_GEN >= 8 anv_batch_emit(&batch, GENX(3DSTATE_WM_CHROMAKEY), ck); -#if GEN_GEN == 10 - gen10_emit_wa_cs_stall_flush(&batch); -#endif - - /* See the Vulkan 1.0 spec Table 24.1 "Standard sample locations" and - * VkPhysicalDeviceFeatures::standardSampleLocations. - */ - anv_batch_emit(&batch, GENX(3DSTATE_SAMPLE_PATTERN), sp) { - GEN_SAMPLE_POS_1X(sp._1xSample); - GEN_SAMPLE_POS_2X(sp._2xSample); - GEN_SAMPLE_POS_4X(sp._4xSample); - GEN_SAMPLE_POS_8X(sp._8xSample); -#if GEN_GEN >= 9 - GEN_SAMPLE_POS_16X(sp._16xSample); -#endif - } + genX(emit_sample_pattern)(&batch); /* The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in the * section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer @@ -167,10 +152,6 @@ genX(init_device_state)(struct anv_device *device) anv_batch_emit(&batch, GENX(3DSTATE_WM_HZ_OP), hzp); #endif -#if GEN_GEN == 10 - gen10_emit_wa_lri_to_cache_mode_zero(&batch); -#endif - #if GEN_GEN == 11 /* The default behavior of bit 5 "Headerless Message for Pre-emptable * Contexts" in SAMPLER MODE register is set to 0, which means @@ -236,6 +217,69 @@ genX(init_device_state)(struct anv_device *device) return anv_device_submit_simple_batch(device, &batch); } +void +genX(emit_multisample)(struct anv_batch *batch, uint32_t samples) +{ + anv_batch_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms) { + ms.NumberofMultisamples = __builtin_ffs(samples) - 1; + + ms.PixelLocation = CENTER; +#if GEN_GEN >= 8 + /* The PRM says that this bit is valid only for DX9: + * + * SW can choose to set this bit only for DX9 API. DX10/OGL API's + * should not have any effect by setting or not setting this bit. + */ + ms.PixelPositionOffsetEnable = false; +#else + + switch (samples) { + case 1: + GEN_SAMPLE_POS_1X(ms.Sample); + break; + case 2: + GEN_SAMPLE_POS_2X(ms.Sample); + break; + case 4: + GEN_SAMPLE_POS_4X(ms.Sample); + break; + case 8: + GEN_SAMPLE_POS_8X(ms.Sample); + break; + default: + break; + } +#endif + } +} + +#if GEN_GEN >= 8 +void +genX(emit_sample_pattern)(struct anv_batch *batch) +{ +#if GEN_GEN == 10 + gen10_emit_wa_cs_stall_flush(batch); +#endif + + /* See the Vulkan 1.0 spec Table 24.1 "Standard sample locations" and + * VkPhysicalDeviceFeatures::standardSampleLocations. + */ + anv_batch_emit(batch, GENX(3DSTATE_SAMPLE_PATTERN), sp) { + GEN_SAMPLE_POS_1X(sp._1xSample); + GEN_SAMPLE_POS_2X(sp._2xSample); + GEN_SAMPLE_POS_4X(sp._4xSample); + GEN_SAMPLE_POS_8X(sp._8xSample); +#if GEN_GEN >= 9 + GEN_SAMPLE_POS_16X(sp._16xSample); +#endif + } + +#if GEN_GEN == 10 + gen10_emit_wa_lri_to_cache_mode_zero(batch); +#endif +} +#endif + static uint32_t vk_to_gen_tex_filter(VkFilter filter, bool anisotropyEnable) { -- 2.20.1 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev