The surface_state setup for renderbuffers already worked; only the
texturing side needed work. BLORP does something similar, but does its
own surface_state setup.
On Gen6, we just need to set the correct sample count.
On Gen7: - set the correct sample count
- set the correct layout mode
- set GEN7_SURFACE_ARYSPC_LOD0 if it's set in the miptree.
V2: - Clarify commit message
- Rebased onto Paul's physical/logical dims cleanup
- Added Gen7 support
Signed-off-by: Chris Forbes <chr...@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype...@gmail.com>
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 9 +++++----
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index e1c82fa..a5b337e 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -871,7 +871,7 @@ brw_update_texture_surface(struct gl_context *ctx,
(intelObj->mt->region->pitch - 1) <<
BRW_SURFACE_PITCH_SHIFT);
- surf[4] = 0;
+ surf[4] = brw_get_surface_num_multisamples(intelObj->mt->num_samples);
intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0,
&tile_x, &tile_y);
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 179024a..874ec2d 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -299,10 +299,6 @@ gen7_update_texture_surface(struct gl_context *ctx,
return;
}
- /* We don't support MSAA for textures. */
- assert(!mt->array_spacing_lod0);
- assert(mt->num_samples <= 1);
-
intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
@@ -327,6 +323,9 @@ gen7_update_texture_surface(struct gl_context *ctx,
if (depth > 1 && tObj->Target != GL_TEXTURE_3D)
surf[0] |= GEN7_SURFACE_IS_ARRAY;
+ if (mt->array_spacing_lod0)
+ surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
+
surf[1] = mt->region->bo->offset + mt->offset; /* reloc */
surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
@@ -334,6 +333,8 @@ gen7_update_texture_surface(struct gl_context *ctx,
surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) |
((intelObj->mt->region->pitch) - 1);
+ surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
+
intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0,
&tile_x, &tile_y);
assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
--
1.8.1.2
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