On Tue, Feb 12, 2013 at 10:45:27PM +0100, Vincent Lejeune wrote: > It fixes around 100 tfb piglit tests and 16 glean tests. > > NOTE: This is a candidate for the Mesa stable branch.
Reviewed-by: Tom Stellard <thomas.stell...@amd.com> > --- > lib/Target/R600/AMDILISelDAGToDAG.cpp | 2 ++ > lib/Target/R600/R600LowerConstCopy.cpp | 2 +- > test/CodeGen/R600/kcache-fold.ll | 52 > ++++++++++++++++++++++++++++++++++ > 3 files changed, 55 insertions(+), 1 deletion(-) > create mode 100644 test/CodeGen/R600/kcache-fold.ll > > diff --git a/lib/Target/R600/AMDILISelDAGToDAG.cpp > b/lib/Target/R600/AMDILISelDAGToDAG.cpp > index 2f34fe3..858eb5d 100644 > --- a/lib/Target/R600/AMDILISelDAGToDAG.cpp > +++ b/lib/Target/R600/AMDILISelDAGToDAG.cpp > @@ -358,6 +358,8 @@ bool AMDGPUDAGToDAGISel::FoldOperands(unsigned Opcode, > SDValue Operand = Ops[OperandIdx[i] - 1]; > switch (Operand.getOpcode()) { > case AMDGPUISD::CONST_ADDRESS: { > + if (i == 2) > + break; > SDValue CstOffset; > if (!Operand.getValueType().isVector() && > SelectGlobalValueConstantOffset(Operand.getOperand(0), CstOffset)) > { > diff --git a/lib/Target/R600/R600LowerConstCopy.cpp > b/lib/Target/R600/R600LowerConstCopy.cpp > index 2557e8f..c8c27a8 100644 > --- a/lib/Target/R600/R600LowerConstCopy.cpp > +++ b/lib/Target/R600/R600LowerConstCopy.cpp > @@ -180,7 +180,7 @@ bool > R600LowerConstCopy::runOnMachineFunction(MachineFunction &MF) { > int ConstMovSel = > TII->getOperandIdx(CstMov->getOpcode(), > R600Operands::SRC0_SEL); > unsigned ConstIndex = CstMov->getOperand(ConstMovSel).getImm(); > - if (canFoldInBundle(CP, ConstIndex)) { > + if (MI->isInsideBundle() && canFoldInBundle(CP, ConstIndex)) { > TII->setImmOperand(MI, OpTable[SrcOp][1], ConstIndex); > MI->getOperand(SrcIdx).setReg(AMDGPU::ALU_CONST); > } else { > diff --git a/test/CodeGen/R600/kcache-fold.ll > b/test/CodeGen/R600/kcache-fold.ll > new file mode 100644 > index 0000000..382f78c > --- /dev/null > +++ b/test/CodeGen/R600/kcache-fold.ll > @@ -0,0 +1,52 @@ > +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s > + > +; CHECK: MOV T{{[0-9]+\.[XYZW], CBuf0\[[0-9]+\]\.[XYZW]}} > + > +define void @main() { > +main_body: > + %0 = load <4 x float> addrspace(9)* null > + %1 = extractelement <4 x float> %0, i32 0 > + %2 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] > addrspace(9)* null, i64 0, i32 1) > + %3 = extractelement <4 x float> %2, i32 0 > + %4 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] > addrspace(9)* null, i64 0, i32 2) > + %5 = extractelement <4 x float> %4, i32 0 > + %6 = fcmp ult float %1, 0.000000e+00 > + %7 = select i1 %6, float %3, float %5 > + %8 = load <4 x float> addrspace(9)* null > + %9 = extractelement <4 x float> %8, i32 1 > + %10 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] > addrspace(9)* null, i64 0, i32 1) > + %11 = extractelement <4 x float> %10, i32 1 > + %12 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] > addrspace(9)* null, i64 0, i32 2) > + %13 = extractelement <4 x float> %12, i32 1 > + %14 = fcmp ult float %9, 0.000000e+00 > + %15 = select i1 %14, float %11, float %13 > + %16 = load <4 x float> addrspace(9)* null > + %17 = extractelement <4 x float> %16, i32 2 > + %18 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] > addrspace(9)* null, i64 0, i32 1) > + %19 = extractelement <4 x float> %18, i32 2 > + %20 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] > addrspace(9)* null, i64 0, i32 2) > + %21 = extractelement <4 x float> %20, i32 2 > + %22 = fcmp ult float %17, 0.000000e+00 > + %23 = select i1 %22, float %19, float %21 > + %24 = load <4 x float> addrspace(9)* null > + %25 = extractelement <4 x float> %24, i32 3 > + %26 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] > addrspace(9)* null, i64 0, i32 1) > + %27 = extractelement <4 x float> %26, i32 3 > + %28 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] > addrspace(9)* null, i64 0, i32 2) > + %29 = extractelement <4 x float> %28, i32 3 > + %30 = fcmp ult float %25, 0.000000e+00 > + %31 = select i1 %30, float %27, float %29 > + %32 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float > 1.000000e+00) > + %33 = call float @llvm.AMDIL.clamp.(float %15, float 0.000000e+00, float > 1.000000e+00) > + %34 = call float @llvm.AMDIL.clamp.(float %23, float 0.000000e+00, float > 1.000000e+00) > + %35 = call float @llvm.AMDIL.clamp.(float %31, float 0.000000e+00, float > 1.000000e+00) > + %36 = insertelement <4 x float> undef, float %32, i32 0 > + %37 = insertelement <4 x float> %36, float %33, i32 1 > + %38 = insertelement <4 x float> %37, float %34, i32 2 > + %39 = insertelement <4 x float> %38, float %35, i32 3 > + call void @llvm.R600.store.swizzle(<4 x float> %39, i32 0, i32 0) > + ret void > +} > + > +declare float @llvm.AMDIL.clamp.(float, float, float) readnone > +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) > -- > 1.8.1.2 > > _______________________________________________ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/mesa-dev _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev