Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_state.h | 7 +++++++
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 13 ++++++++++++-
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 4 +++-
3 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index f32597d..fef659b 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -212,6 +212,13 @@ struct brw_wm_surface {
uint32_t page_offset;
unsigned min_lod;
unsigned mip_count;
+
+ /* Offsets within tile. These are needed when mip-level and/or layer
+ * are accessed without native hardware support. Page offset is adjusted
+ * with full pages and the remaining is accounted for here.
+ */
+ unsigned tile_x;
+ unsigned tile_y;
};
void gen4_init_vtable_surface_functions(struct brw_context *brw);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index a27fad1..6f23cec 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -209,10 +209,19 @@ brw_get_texture_surface(const struct gl_texture_object
*tex_obj,
surface->page_offset = 0;
surface->min_lod = tex_obj->BaseLevel - mt->first_level;
surface->mip_count = intel_tex->_MaxLevel - tex_obj->BaseLevel;
+ surface->tile_x = 0;
+ surface->tile_y = 0;
}
surface->page_offset += mt->offset;
+ /* Note that the low bits of these fields are missing, so there's the
+ * possibility of getting in trouble. Hardware wants width as multiples
+ * of four and height of two.
+ */
+ assert(surface->tile_x % 4 == 0);
+ assert(surface->tile_y % 2 == 0);
+
return mt;
}
@@ -360,7 +369,9 @@ brw_update_texture_surface(struct gl_context *ctx,
surf[4] = (brw_get_surface_num_multisamples(mt->num_samples) |
SET_FIELD(tex.min_lod, BRW_SURFACE_MIN_LOD));
- surf[5] = mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
+ surf[5] = SET_FIELD(tex.tile_x / 4, BRW_SURFACE_X_OFFSET) |
+ SET_FIELD(tex.tile_y / 2, BRW_SURFACE_Y_OFFSET) |
+ (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0);
/* Emit relocation to surface contents */
drm_intel_bo_emit_reloc(brw->batch.bo,
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 8389dcf..e7baa81 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -325,7 +325,9 @@ gen7_update_texture_surface(struct gl_context *ctx,
surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
- surf[5] = SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) |
+ surf[5] = SET_FIELD(tex.tile_x / 4, BRW_SURFACE_X_OFFSET) |
+ SET_FIELD(tex.tile_y / 2, BRW_SURFACE_Y_OFFSET) |
+ SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) |
SET_FIELD(tex.min_lod, GEN7_SURFACE_MIN_LOD) |
tex.mip_count;
--
1.8.3.1
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