Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_state.h | 16 ++++++++
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 49 ++++++++++++++++++-----
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 27 ++++++-------
3 files changed, 67 insertions(+), 25 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index 72478ba..f32597d 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -202,6 +202,18 @@ void *brw_state_batch(struct brw_context *brw,
uint32_t *out_offset);
/* brw_wm_surface_state.c */
+
+struct brw_wm_surface {
+ uint32_t tiling;
+ unsigned width;
+ unsigned height;
+ unsigned depth;
+ unsigned pitch;
+ uint32_t page_offset;
+ unsigned min_lod;
+ unsigned mip_count;
+};
+
void gen4_init_vtable_surface_functions(struct brw_context *brw);
uint32_t brw_get_surface_tiling_bits(uint32_t tiling);
uint32_t brw_get_surface_num_multisamples(unsigned num_samples);
@@ -217,6 +229,10 @@ GLuint translate_tex_format(struct brw_context *brw,
int brw_get_texture_swizzle(const struct gl_context *ctx,
const struct gl_texture_object *t);
+const struct intel_mipmap_tree *
+brw_get_texture_surface(const struct gl_texture_object *tex_obj,
+ struct brw_wm_surface *surface);
+
/* gen7_wm_surface_state.c */
unsigned brw_swizzle_to_scs(GLenum swizzle, bool need_green_to_blue);
uint32_t gen7_surface_tiling_mode(uint32_t tiling);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 73acae5..a27fad1 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -190,6 +190,32 @@ brw_get_texture_swizzle(const struct gl_context *ctx,
swizzles[GET_SWZ(t->_Swizzle, 3)]);
}
+const struct intel_mipmap_tree *
+brw_get_texture_surface(const struct gl_texture_object *tex_obj,
+ struct brw_wm_surface *surface)
+{
+ const struct intel_texture_object *intel_tex =
intel_texture_object(tex_obj);
+ const struct gl_texture_image *first =
tex_obj->Image[0][tex_obj->BaseLevel];
+ const struct intel_mipmap_tree *mt = intel_tex->mt;
+
+ if (tex_obj->StencilSampling && first->_BaseFormat == GL_DEPTH_STENCIL) {
+ assert(!"Stencil indexing shouldn't be enabled yet");
+ } else {
+ surface->tiling = mt->region->tiling;
+ surface->width = mt->logical_width0;
+ surface->height = mt->logical_height0;
+ surface->depth = mt->logical_depth0;
+ surface->pitch = mt->region->pitch;
+ surface->page_offset = 0;
+ surface->min_lod = tex_obj->BaseLevel - mt->first_level;
+ surface->mip_count = intel_tex->_MaxLevel - tex_obj->BaseLevel;
+ }
+
+ surface->page_offset += mt->offset;
+
+ return mt;
+}
+
static void
gen4_emit_buffer_surface_state(struct brw_context *brw,
uint32_t *out_offset,
@@ -268,9 +294,9 @@ brw_update_texture_surface(struct gl_context *ctx,
{
struct brw_context *brw = brw_context(ctx);
struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
- struct intel_texture_object *intelObj = intel_texture_object(tObj);
- struct intel_mipmap_tree *mt = intelObj->mt;
struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
+ const struct intel_mipmap_tree *mt;
+ struct brw_wm_surface tex;
uint32_t *surf;
/* BRW_NEW_UNIFORM_BUFFER */
@@ -279,6 +305,8 @@ brw_update_texture_surface(struct gl_context *ctx,
return;
}
+ mt = brw_get_texture_surface(tObj, &tex);
+
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
6 * 4, 32, surf_offset);
@@ -319,19 +347,18 @@ brw_update_texture_surface(struct gl_context *ctx,
BRW_SURFACE_CUBEFACE_ENABLES |
tex_format << BRW_SURFACE_FORMAT_SHIFT);
- surf[1] = mt->region->bo->offset64 + mt->offset; /* reloc */
+ surf[1] = mt->region->bo->offset64 + tex.page_offset; /* reloc */
- surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT
|
- (mt->logical_width0 - 1) << BRW_SURFACE_WIDTH_SHIFT |
- (mt->logical_height0 - 1) << BRW_SURFACE_HEIGHT_SHIFT);
+ surf[2] = SET_FIELD(tex.mip_count, BRW_SURFACE_LOD) |
+ SET_FIELD(tex.width - 1, BRW_SURFACE_WIDTH) |
+ SET_FIELD(tex.height - 1, BRW_SURFACE_HEIGHT);
- surf[3] = (brw_get_surface_tiling_bits(mt->region->tiling) |
- (mt->logical_depth0 - 1) << BRW_SURFACE_DEPTH_SHIFT |
- (mt->region->pitch - 1) <<
- BRW_SURFACE_PITCH_SHIFT);
+ surf[3] = brw_get_surface_tiling_bits(tex.tiling) |
+ SET_FIELD(tex.depth - 1, BRW_SURFACE_DEPTH) |
+ SET_FIELD(tex.pitch - 1, BRW_SURFACE_PITCH);
surf[4] = (brw_get_surface_num_multisamples(mt->num_samples) |
- SET_FIELD(tObj->BaseLevel - mt->first_level,
BRW_SURFACE_MIN_LOD));
+ SET_FIELD(tex.min_lod, BRW_SURFACE_MIN_LOD));
surf[5] = mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 9d9c375..8389dcf 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -275,16 +275,18 @@ gen7_update_texture_surface(struct gl_context *ctx,
{
struct brw_context *brw = brw_context(ctx);
struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
- struct intel_texture_object *intelObj = intel_texture_object(tObj);
- struct intel_mipmap_tree *mt = intelObj->mt;
struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
+ const struct intel_mipmap_tree *mt;
+ struct brw_wm_surface tex;
if (tObj->Target == GL_TEXTURE_BUFFER) {
brw_update_buffer_texture_surface(ctx, unit, surf_offset);
return;
}
+ mt = brw_get_texture_surface(tObj, &tex);
+
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
8 * 4, 32, surf_offset);
memset(surf, 0, 8 * 4);
@@ -298,7 +300,7 @@ gen7_update_texture_surface(struct gl_context *ctx,
surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
tex_format << BRW_SURFACE_FORMAT_SHIFT |
- gen7_surface_tiling_mode(mt->region->tiling);
+ gen7_surface_tiling_mode(tex.tiling);
/* mask of faces present in cube map; for other surfaces MBZ. */
if (tObj->Target == GL_TEXTURE_CUBE_MAP || tObj->Target ==
GL_TEXTURE_CUBE_MAP_ARRAY)
@@ -309,26 +311,23 @@ gen7_update_texture_surface(struct gl_context *ctx,
if (mt->align_w == 8)
surf[0] |= GEN7_SURFACE_HALIGN_8;
- if (mt->logical_depth0 > 1 && tObj->Target != GL_TEXTURE_3D)
+ if (tex.depth > 1 && tObj->Target != GL_TEXTURE_3D)
surf[0] |= GEN7_SURFACE_IS_ARRAY;
if (mt->array_spacing_lod0)
surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
- surf[1] = mt->region->bo->offset64 + mt->offset; /* reloc */
+ surf[1] = mt->region->bo->offset64 + tex.page_offset; /* reloc */
- surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
- SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
- surf[3] = SET_FIELD(mt->logical_depth0 - 1, BRW_SURFACE_DEPTH) |
- (mt->region->pitch - 1);
+ surf[2] = SET_FIELD(tex.width - 1, GEN7_SURFACE_WIDTH) |
+ SET_FIELD(tex.height - 1, GEN7_SURFACE_HEIGHT);
+ surf[3] = SET_FIELD(tex.depth - 1, BRW_SURFACE_DEPTH) | (tex.pitch - 1);
surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
- surf[5] = (SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) |
- SET_FIELD(tObj->BaseLevel - mt->first_level,
- GEN7_SURFACE_MIN_LOD) |
- /* mip count */
- (intelObj->_MaxLevel - tObj->BaseLevel));
+ surf[5] = SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) |
+ SET_FIELD(tex.min_lod, GEN7_SURFACE_MIN_LOD) |
+ tex.mip_count;
if (brw->is_haswell) {
/* Handling GL_ALPHA as a surface format override breaks 1.30+ style
--
1.8.3.1
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