This is the first chunk of patches in my work on adding instruction and register widths to the fs backend. Eventually, this will allow us to more easily emit 8-wide instructions in SIMD16 mode from the fs_visitor level. More patches will be coming to add a width field to the registers and allow for more fine-grained register allocation.
I talked to Ken in the office today about maybe delaying these patches until later, but they turned out pretty clean so I decided to send them now. At each commit in the series there are 0 piglit chages from master on HSW. Jason Ekstrand (10): i965/fs: Clean up emitting of untyped atomic and sruface reads i965/fs: Add a width field to fs_inst i965/fs: Properly set the instruction width for atomics and surface reads i965/fs: Set instruction widths in a variety of places i965/fs: Derive force_uncompressed from instruction width i965/fs: Remove unneeded uses of force_uncompressed i965/fs: Use instruction widths to set compression state i965/fs: Use instruction width instead of heuristics i965/fs: Determine partial writes with instruction widths i965/fs: Use instruction width directly for texture generation src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 10 +- src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h | 34 +++--- src/mesa/drivers/dri/i965/brw_fs.cpp | 116 +++++++++++---------- src/mesa/drivers/dri/i965/brw_fs.h | 30 ++++-- src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 33 ++++-- .../drivers/dri/i965/brw_fs_live_variables.cpp | 10 +- src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 8 +- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 54 +++++----- .../drivers/dri/i965/brw_schedule_instructions.cpp | 4 +- 9 files changed, 165 insertions(+), 134 deletions(-) -- 2.1.0 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev