From: Francisco Jerez <curroje...@riseup.net>
Allow for pipelined register writes for gen < 7.
v2:
* Split from another patch and adjust comment (jljusten)
Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com>
---
src/mesa/drivers/dri/i965/intel_extensions.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index f70f403..81215db 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -40,8 +40,11 @@
static bool
can_do_pipelined_register_writes(struct brw_context *brw)
{
- /* Supposedly, Broadwell just works. */
- if (brw->gen >= 8)
+ /**
+ * gen >= 8 specifically allows these writes. gen <= 6 also
+ * doesn't block them.
+ */
+ if (brw->gen != 7)
return true;
static int result = -1;
--
2.6.2
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