I'm looking at r600/r700 compiler with the ambition of filling in the missing pieces. I've just read through the documentation and the basic structure of the compiler, and I'm having a hard time understanding the design choices of the code. Hopefully someone can fill me in on what the plan is here.
The basic problem is that the compiler is a somewhat poor fit for the
hardware. The compiler is designed around vectors, whilst the hardware
works more in terms of individual elements (albeit with a whole bunch
of restrictions). This disparity means that the compiler in its current
form can be very inefficient. Worst case scenario is using 25% of the
hardware.
As an example, I've been looking at implementing the EXP op. A simple
implementation would use 4 instruction groups with the current
compiler, but the hardware should be capable of doing it with 2. An
optimised implementation would range in efficiency between 100% and 33%
of hardware capability. The common case would probably still be 50%.
So what's the plan here? This kind of inefficiency must be a temporary
solution and not the final goal?
Rgds
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-- Pierre Ossman
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