It would help a lot if you'd disclose what chip you're trying to communicate
with. (My wild guess would be a maxim ultrasound chip, am I far of the mark here?)
Are you sure this isn't just compatible with existing SPI mode/phase settings?
And you have a huge FPGA at your disposal if you have a Xilinx device of any
kind. I'd suggest just solving this in a bit of FPGA logic instead of in
userspace C code.
On 09-05-17 14:54, Arno Steffens wrote:
I have a rather strange SPI protocol to run: write and read use different edges
to sample.
See image:
I configured the spi like that:
static u8 mode_wr = 0;
static u8 mode_rd = 1;
ret = ioctl(file_spi0, SPI_IOC_WR_MODE, &mode_wr);
if (ret == -1)
printf("can't set spi mode");
ret = ioctl(file_spi0, SPI_IOC_RD_MODE, &mode_rd);
if (ret == -1)
printf("can't get spi mode");
The transfer itself runs via:
ret = ioctl(file_spi0, SPI_IOC_MESSAGE(1), &transfer);
But it seems, that only SPI_IOC_WR_MODE has an effect for both, write and read.
Is this a limitation of hardware, bug in driver or my bug?
So I have to chose either sending correct address or receive correct data.
For only mode=1 and adress=0 it works fully (as with constant 0 sampling edge
is not of importance).
(as in the struct spi_ioc_transfer only bits_per_word = 8 are allowed, I use a
4 byte transfer (32bit) for these 9+1+16=26 bit.)
From what I see in Osci this seems to be fine, although it is some bit-fiddling.
Best regards
Arno
Kind regards,
Mike Looijmans
System Expert
TOPIC Products
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