Add tune file supporting versal devices. Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency
Signed-off-by: Alejandro Enedino Hernandez Samaniego <aleja...@xilinx.com> Signed-off-by: Manjukumar Matha <manjukumar.harthikote-ma...@xilinx.com> --- meta-xilinx-bsp/conf/machine/include/tune-versal.inc | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 meta-xilinx-bsp/conf/machine/include/tune-versal.inc diff --git a/meta-xilinx-bsp/conf/machine/include/tune-versal.inc b/meta-xilinx-bsp/conf/machine/include/tune-versal.inc new file mode 100644 index 0000000..83acf6e --- /dev/null +++ b/meta-xilinx-bsp/conf/machine/include/tune-versal.inc @@ -0,0 +1,14 @@ +DEFAULTTUNE ?= "aarch64" +SOC_FAMILY ?= "versal" + +# Available SOC_VARIANT's for versal: +# virt + +SOC_VARIANT ?= "" + +require conf/machine/include/arm/arch-armv8.inc +require conf/machine/include/soc-family.inc + +# Linux Configuration +KERNEL_IMAGETYPE ?= "Image" + -- 2.7.4 -- _______________________________________________ meta-xilinx mailing list meta-xilinx@yoctoproject.org https://lists.yoctoproject.org/listinfo/meta-xilinx
