On Tuesday 03 March 2009 22:19:16 Cactus wrote: > On Mar 3, 10:09 pm, Bill Hart <goodwillh...@googlemail.com> wrote: > > Scale that and it's only 1-1.5% behind the linux benches. Maybe > > Brian's laptop is working to rule. > > Its a Microsoft tax :-) > > Brian > >
I've heard somewhere that if you are not running on all the cores on a chip , then the clock frequency can be increased and still keep within the same overal thermal envelope. I dont know if thats core2 or not , perhaps core i7 ? The K8 graphs are remarkibly smooth , notice the branch misprediction penalty kicking in at 36=9*4 limbs for mpn_add_n , dont know what that kink is on the mul_basecase though? The core2 add is all over place . This reminds me of mpn_com_n on K8 before I fixed the bank conflict in the L1 cache , I suppose core2 suffers from it as well , and our mpn_add_n hits it. Jason --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "mpir-devel" group. To post to this group, send email to mpir-devel@googlegroups.com To unsubscribe from this group, send email to mpir-devel+unsubscr...@googlegroups.com For more options, visit this group at http://groups.google.com/group/mpir-devel?hl=en -~----------~----~----~----~------~----~------~--~---
