On Sunday 15 March 2009 01:32:23 Bill Hart wrote:
> I was thinking of the original yasm one we had from converting
> Pierrick Gaudry's code, i.e. what was there before we switched to your
> code. It was probably in the amd64 directory before you revolutionised
> it.
>
> Bill.
>

Done 



> 2009/3/15 Jason Moxham <ja...@njkfrudils.plus.com>:
> > On Sunday 15 March 2009 00:49:33 Bill Hart wrote:
> >> We can do similar to Brian and put the old assembler in for add_n and
> >> sub_n for nocona.
> >
> > svn, and commited ,  the nocona with no lahf will use mpn/x86_64/add_n.as
> > , which at the moment is GMP's old one.I assume you mean an other one.
> >
> >> Heh, I've just been reading instruction sets for old CPU's. I think
> >> the 8086 must have been the first main processor of Intel's to have a
> >> mul instruction. I hadn't realised that.
> >>
> >> I wonder if there were earlier processors made by other manufacturers,
> >> but used in home computers or games machines that had them.
> >>
> >> Bill.
> >>
> >> 2009/3/15 Jason Moxham <ja...@njkfrudils.plus.com>:
> >> > On Saturday 14 March 2009 23:11:07 Bill Hart wrote:
> >> >> I think we should examine the feature flag in config.guess for
> >> >> LAHF-SAHF. Here is an incomplete list of 64 bit Pentium 4's without
> >> >> the feature:
> >> >>
> >> >> Pentium 4 506 E0
> >> >> Pentium 4 516 E0
> >> >> Pentium 4 511 E0
> >> >> Pentium 4 519K E0
> >> >> Pentium 4 HT 521
> >> >> Pentium 4 HT 531
> >> >> Pentium 4 HT 541
> >> >> Pentium 4 HT 551
> >> >> Pentium 4 HT 561
> >> >> Pentium 4 HT 571
> >> >> Pentium 4 HT 3.2F
> >> >> Pentium 4 HT 3.4F
> >> >> Pentium 4 HT 3.6F
> >> >> Pentium 4 HT 3.8F
> >> >> Pentium 4 HT 517
> >> >> Pentium 4 HT 524
> >> >> All Family 15, Model 4, steppings N0, R0
> >> >> Pentium 4 EE 3.73
> >> >>
> >> >> Too messy to test for them all specially.
> >> >>
> >> >> Can we add a directory called LAHF to core2 and have all nocona
> >> >> processors use only core2 in the build whereas specifically core2
> >> >> processors can use core2 and core2/lahf. It will be the simplest fix
> >> >> for now until we can implement something more sophisticated.
> >> >
> >> > Sounds good , give us 30 mins to do it
> >> >
> >> >> Bill.
> >> >>
> >> >> 2009/3/14 Jason Moxham <ja...@njkfrudils.plus.com>:
> >> >> > Early Intel CPUs with Intel 64 lacked LAHF and SAHF instructions
> >> >> > available in AMD64 until introduction of Pentium 4 G1 step in
> >> >> > December 2005. LAHF and SAHF are load and store instructions,
> >> >> > respectively, for certain status flags. These instructions are used
> >> >> > for virtualization and floating-point condition handling.
> >> >> >
> >> >> >
> >> >> > I'll  find out model numbers soon
> >> >> >
> >> >> > On Saturday 14 March 2009 17:20:25 Gonzalo Tornaria wrote:
> >> >> >> On Sat, Mar 14, 2009 at 1:45 PM, Jason Moxham
> >> >> >> <ja...@njkfrudils.plus.com>
> >> >> >
> >> >> > wrote:
> >> >> >> > I pretty sure all core2 cpus have lahf,sahf , it's just some
> >> >> >> > Pentium D dont have it . You can test the lahf_lm feature bit in
> >> >> >> > cpuid to see if it's got it
> >> >> >>
> >> >> >> Tested in:
> >> >> >>
> >> >> >> My laptop: model 6 / family 15 (core 2 duo T5300).
> >> >> >> My desktop is family 15 / model 6 (pentium D 930).
> >> >> >>
> >> >> >> The "lahf_lm" feature is present in both according to
> >> >> >> /proc/cpuinfo.
> >> >> >>
> >> >> >> Note that the laptop is "low end" core 2 (in the sense it has no
> >> >> >> VT extensions). The pentium D is "high end" (in the sense it has
> >> >> >> VT extensions --- low end would be pentium D 8xx). Maybe that
> >> >> >> makes a difference?
> >> >> >>
> >> >> >> OTOH, the kvm 64 bit virtual cpu (kvm 72) doesn't seem to know
> >> >> >> about the "lahf_lm" (meaning, it won't report it in cpuid, even if
> >> >> >> the host processor has it. I assume the instructions would work
> >> >> >> anyway.)
> >> >> >>
> >> >> >> Gonzalo
>
> 


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