Attached are tuning values for nehalem, ivybridge, broadwell and skylake.
(Also cpuinfo for the broadwell one)
Isuru Fernado
On Tue, Feb 14, 2017 at 1:29 PM, 'Bill Hart' via mpir-devel <
mpir-devel@googlegroups.com> wrote:
> Apparently if you have a very recent machine, yasm may fail to build the
> assembly files for your architecture. To get around this, install the
> latest yasm [1] and use MPIR's --with-system-yasm option.
>
> If your system is recent and detects as core2 or k8 or simply x86_64 or
> something else obviously out-of-date, when tuning, please also send us a
> copy of cat /proc/cpuinfo so we can add support for your processor to MPIR.
>
> Bill.
>
> [1] http://yasm.tortall.net/
>
> On 13 February 2017 at 18:41, Bill Hart <goodwillh...@googlemail.com>
> wrote:
>
>> Hi all,
>>
>> MPIR has been modified recently, and new tuning crossovers have been
>> added.
>>
>> If you have a machine that you want MPIR to run fast on, we would really
>> appreciate help getting tuning values for your machine. Here is how.
>>
>> git clone https://github.com/wbhart/mpir
>> cd mpir
>> ./configure --enable-gmpcompat
>> make -j4
>> make check
>> cd tune
>> make tune
>>
>> Please attach the tuning values that are printed to this post. Please
>> ensure that the first line is not missing, e.g.
>>
>> Parameters for ./mpn/x86_64/k8/k10/k102/gmp-mparam.h
>>
>> as this tells us what machine the values are for.
>>
>> If the tuning program crashes, or starts to take too long, just send us
>> the values you have.
>>
>> Any help that people can provide is really appreciated.
>>
>> Note that we DON'T require tuning values for the following arches:
>>
>> mpn/x86_64/k8/k10/k102
>> mpn/x86_64/haswell
>>
>> If someone already attached values for your arch, no need to supply them
>> again.
>>
>> Bill.
>>
>>
> --
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Parameters for ./mpn/x86_64/nehalem/gmp-mparam.h
Using: CPU cycle counter, supplemented by microsecond getrusage()
speed_precision 1000000, speed_unittime 6.27e-10 secs, CPU freq 1596.00 MHz
DEFAULT_MAX_SIZE 1000, fft_max_size 50000
/* Generated by tuneup.c, 2017-02-14, gcc 5.4 */
#define MUL_KARATSUBA_THRESHOLD 16
#define MUL_TOOM3_THRESHOLD 89
#define MUL_TOOM4_THRESHOLD 166
#define MUL_TOOM8H_THRESHOLD 286
#define SQR_BASECASE_THRESHOLD 0 /* always (native) */
#define SQR_KARATSUBA_THRESHOLD 24
#define SQR_TOOM3_THRESHOLD 93
#define SQR_TOOM4_THRESHOLD 278
#define SQR_TOOM8_THRESHOLD 351
#define DIVREM_1_NORM_THRESHOLD MP_SIZE_T_MAX /* never */
#define DIVREM_1_UNNORM_THRESHOLD MP_SIZE_T_MAX /* never */
#define MOD_1_NORM_THRESHOLD 0 /* always */
#define MOD_1_UNNORM_THRESHOLD 0 /* always */
#define USE_PREINV_DIVREM_1 1 /* native */
#define USE_PREINV_MOD_1 1
#define DIVEXACT_1_THRESHOLD 0 /* always */
#define MODEXACT_1_ODD_THRESHOLD 0 /* always (native) */
#define MOD_1_1_THRESHOLD 5
#define MOD_1_2_THRESHOLD 8
#define MOD_1_3_THRESHOLD 16
#define DIVREM_HENSEL_QR_1_THRESHOLD 10
#define RSH_DIVREM_HENSEL_QR_1_THRESHOLD 7
#define DIVREM_EUCLID_HENSEL_THRESHOLD 119
#define MUL_FFT_FULL_THRESHOLD 3008
#define SQR_FFT_FULL_THRESHOLD 2368
#define MULLOW_BASECASE_THRESHOLD 0 /* always */
#define MULLOW_DC_THRESHOLD 41
#define MULLOW_MUL_THRESHOLD 3402
#define MULMID_TOOM42_THRESHOLD 24
#define MULHIGH_BASECASE_THRESHOLD 8
#define MULHIGH_DC_THRESHOLD 35
#define MULHIGH_MUL_THRESHOLD 2716
#define MULMOD_2EXPM1_THRESHOLD 14
#define DC_DIV_QR_THRESHOLD 32
#define INV_DIV_QR_THRESHOLD 1895
#define INV_DIVAPPR_Q_N_THRESHOLD 32
#define DC_DIV_Q_THRESHOLD 44
#define INV_DIV_Q_THRESHOLD 1142
#define DC_DIVAPPR_Q_THRESHOLD 38
#define INV_DIVAPPR_Q_THRESHOLD 16039
#define DC_BDIV_QR_THRESHOLD 36
#define DC_BDIV_Q_THRESHOLD 11
#define BINV_NEWTON_THRESHOLD 22
#define REDC_1_TO_REDC_2_THRESHOLD 2
#define REDC_2_TO_REDC_N_THRESHOLD 44
#define ROOTREM_THRESHOLD 6
#define MATRIX22_STRASSEN_THRESHOLD 13
#define HGCD_THRESHOLD 86
#define HGCD_APPR_THRESHOLD 50
#define HGCD_REDUCE_THRESHOLD 6852
#define GCD_DC_THRESHOLD 386
#define GCDEXT_DC_THRESHOLD 278
#define JACOBI_BASE_METHOD 1
#define GET_STR_DC_THRESHOLD 13
#define GET_STR_PRECOMPUTE_THRESHOLD 18
#define SET_STR_DC_THRESHOLD 172
#define SET_STR_PRECOMPUTE_THRESHOLD 1566
#define FAC_DSC_THRESHOLD 276
#define FAC_ODD_THRESHOLD 43
/* fft_tuning -- autogenerated by tune-fft */
#define FFT_TAB \
{ { 4, 3 }, { 3, 3 }, { 3, 2 }, { 2, 1 }, { 1, 0 } }
#define MULMOD_TAB \
{ 4, 3, 3, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1 }
#define FFT_N_NUM 19
#define FFT_MULMOD_2EXPP1_CUTOFF 128
/* Tuneup completed successfully, took 107 seconds */
Parameters for ./mpn/x86_64/skylake/avx/gmp-mparam.h
Using: CPU cycle counter, supplemented by microsecond getrusage()
speed_precision 1000000, speed_unittime 5.13e-10 secs, CPU freq 1948.09 MHz
DEFAULT_MAX_SIZE 1000, fft_max_size 50000
/* Generated by tuneup.c, 2017-02-14, gcc 5.4 */
#define MUL_KARATSUBA_THRESHOLD 19
#define MUL_TOOM3_THRESHOLD 137
#define MUL_TOOM4_THRESHOLD 193
#define MUL_TOOM8H_THRESHOLD 381
#define SQR_BASECASE_THRESHOLD 0 /* always (native) */
#define SQR_KARATSUBA_THRESHOLD 32
#define SQR_TOOM3_THRESHOLD 89
#define SQR_TOOM4_THRESHOLD 258
#define SQR_TOOM8_THRESHOLD 494
#define DIVREM_1_NORM_THRESHOLD MP_SIZE_T_MAX /* never */
#define DIVREM_1_UNNORM_THRESHOLD MP_SIZE_T_MAX /* never */
#define MOD_1_NORM_THRESHOLD 0 /* always */
#define MOD_1_UNNORM_THRESHOLD 0 /* always */
#define USE_PREINV_DIVREM_1 1 /* native */
#define USE_PREINV_MOD_1 1
#define DIVEXACT_1_THRESHOLD 0 /* always */
#define MODEXACT_1_ODD_THRESHOLD 0 /* always (native) */
#define MOD_1_1_THRESHOLD 6
#define MOD_1_2_THRESHOLD 10
#define MOD_1_3_THRESHOLD 17
#define DIVREM_HENSEL_QR_1_THRESHOLD 31
#define RSH_DIVREM_HENSEL_QR_1_THRESHOLD 6
#define DIVREM_EUCLID_HENSEL_THRESHOLD 35
#define MUL_FFT_FULL_THRESHOLD 5056
#define SQR_FFT_FULL_THRESHOLD 3008
#define MULLOW_BASECASE_THRESHOLD 0 /* always */
#define MULLOW_DC_THRESHOLD 21
#define MULLOW_MUL_THRESHOLD 3369
#define MULMID_TOOM42_THRESHOLD 24
#define MULHIGH_BASECASE_THRESHOLD 10
#define MULHIGH_DC_THRESHOLD 22
#define MULHIGH_MUL_THRESHOLD 3336
#define MULMOD_2EXPM1_THRESHOLD 18
#define DC_DIV_QR_THRESHOLD 29
#define INV_DIV_QR_THRESHOLD 2444
#define INV_DIVAPPR_Q_N_THRESHOLD 29
#define DC_DIV_Q_THRESHOLD 45
#define INV_DIV_Q_THRESHOLD 1258
#define DC_DIVAPPR_Q_THRESHOLD 104
#define INV_DIVAPPR_Q_THRESHOLD 14091
#define DC_BDIV_QR_THRESHOLD 62
#define DC_BDIV_Q_THRESHOLD 96
#define BINV_NEWTON_THRESHOLD 8
#define REDC_1_TO_REDC_2_THRESHOLD 22
#define REDC_2_TO_REDC_N_THRESHOLD 36
#define ROOTREM_THRESHOLD 6
#define MATRIX22_STRASSEN_THRESHOLD 15
#define HGCD_THRESHOLD 103
#define HGCD_APPR_THRESHOLD 98
#define HGCD_REDUCE_THRESHOLD 6852
#define GCD_DC_THRESHOLD 752
#define GCDEXT_DC_THRESHOLD 496
#define JACOBI_BASE_METHOD 2
#define GET_STR_DC_THRESHOLD 14
#define GET_STR_PRECOMPUTE_THRESHOLD 20
#define SET_STR_DC_THRESHOLD 2324
#define SET_STR_PRECOMPUTE_THRESHOLD 3246
#define FAC_DSC_THRESHOLD 858
#define FAC_ODD_THRESHOLD 44
/* fft_tuning -- autogenerated by tune-fft */
#define FFT_TAB \
{ { 4, 4 }, { 4, 3 }, { 3, 2 }, { 3, 2 }, { 2, 1 } }
#define MULMOD_TAB \
{ 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1 }
#define FFT_N_NUM 19
#define FFT_MULMOD_2EXPP1_CUTOFF 256
/* Tuneup completed successfully, took 63 seconds */
Parameters for ./mpn/x86_64/sandybridge/ivybridge/gmp-mparam.h
Using: CPU cycle counter, supplemented by microsecond getrusage()
speed_precision 1000000, speed_unittime 5.01e-10 secs, CPU freq 1995.22 MHz
DEFAULT_MAX_SIZE 1000, fft_max_size 50000
/* Generated by tuneup.c, 2017-02-14, gcc 5.4 */
#define MUL_KARATSUBA_THRESHOLD 16
#define MUL_TOOM3_THRESHOLD 101
#define MUL_TOOM4_THRESHOLD 244
#define MUL_TOOM8H_THRESHOLD 303
#define SQR_BASECASE_THRESHOLD 0 /* always (native) */
#define SQR_KARATSUBA_THRESHOLD 24
#define SQR_TOOM3_THRESHOLD 137
#define SQR_TOOM4_THRESHOLD 250
#define SQR_TOOM8_THRESHOLD 333
#define DIVREM_1_NORM_THRESHOLD MP_SIZE_T_MAX /* never */
#define DIVREM_1_UNNORM_THRESHOLD MP_SIZE_T_MAX /* never */
#define MOD_1_NORM_THRESHOLD 0 /* always */
#define MOD_1_UNNORM_THRESHOLD 0 /* always */
#define USE_PREINV_DIVREM_1 1 /* native */
#define USE_PREINV_MOD_1 1
#define DIVEXACT_1_THRESHOLD 0 /* always */
#define MODEXACT_1_ODD_THRESHOLD 0 /* always (native) */
#define MOD_1_1_THRESHOLD 6
#define MOD_1_2_THRESHOLD 8
#define MOD_1_3_THRESHOLD 17
#define DIVREM_HENSEL_QR_1_THRESHOLD 10
#define RSH_DIVREM_HENSEL_QR_1_THRESHOLD 3
#define DIVREM_EUCLID_HENSEL_THRESHOLD 202
#define MUL_FFT_FULL_THRESHOLD 3776
#define SQR_FFT_FULL_THRESHOLD 2496
#define MULLOW_BASECASE_THRESHOLD 0 /* always */
#define MULLOW_DC_THRESHOLD 75
#define MULLOW_MUL_THRESHOLD 4994
#define MULMID_TOOM42_THRESHOLD 22
#define MULHIGH_BASECASE_THRESHOLD 8
#define MULHIGH_DC_THRESHOLD 35
#define MULHIGH_MUL_THRESHOLD 3436
#define MULMOD_2EXPM1_THRESHOLD 14
#define DC_DIV_QR_THRESHOLD 28
#define INV_DIV_QR_THRESHOLD 2089
#define INV_DIVAPPR_Q_N_THRESHOLD 28
#define DC_DIV_Q_THRESHOLD 44
#define INV_DIV_Q_THRESHOLD 1470
#define DC_DIVAPPR_Q_THRESHOLD 47
#define INV_DIVAPPR_Q_THRESHOLD 17327
#define DC_BDIV_QR_THRESHOLD 25
#define DC_BDIV_Q_THRESHOLD 48
#define BINV_NEWTON_THRESHOLD 48
#define REDC_1_TO_REDC_2_THRESHOLD 18
#define REDC_2_TO_REDC_N_THRESHOLD 36
#define ROOTREM_THRESHOLD 6
#define MATRIX22_STRASSEN_THRESHOLD 19
#define HGCD_THRESHOLD 88
#define HGCD_APPR_THRESHOLD 52
#define HGCD_REDUCE_THRESHOLD 6852
#define GCD_DC_THRESHOLD 483
#define GCDEXT_DC_THRESHOLD 321
#define JACOBI_BASE_METHOD 2
#define GET_STR_DC_THRESHOLD 12
#define GET_STR_PRECOMPUTE_THRESHOLD 23
#define SET_STR_DC_THRESHOLD 1182
#define SET_STR_PRECOMPUTE_THRESHOLD 2342
#define FAC_DSC_THRESHOLD 542
#define FAC_ODD_THRESHOLD 26
/* fft_tuning -- autogenerated by tune-fft */
#define FFT_TAB \
{ { 4, 3 }, { 3, 3 }, { 3, 2 }, { 2, 1 }, { 1, 0 } }
#define MULMOD_TAB \
{ 4, 3, 3, 4, 4, 2, 3, 3, 3, 2, 2, 3, 3, 2, 2, 3, 2, 1, 1 }
#define FFT_N_NUM 19
#define FFT_MULMOD_2EXPP1_CUTOFF 128
/* Tuneup completed successfully, took 129 seconds */
Parameters for ./mpn/x86_64/gmp-mparam.h
Using: CPU cycle counter, supplemented by microsecond getrusage()
speed_precision 1000000, speed_unittime 3.88e-10 secs, CPU freq 2579.76 MHz
DEFAULT_MAX_SIZE 1000, fft_max_size 50000
/* Generated by tuneup.c, 2017-02-14, gcc 5.4 */
#define MUL_KARATSUBA_THRESHOLD 18
#define MUL_TOOM3_THRESHOLD 63
#define MUL_TOOM4_THRESHOLD 166
#define MUL_TOOM8H_THRESHOLD 396
#define SQR_BASECASE_THRESHOLD 0 /* always (native) */
#define SQR_KARATSUBA_THRESHOLD 51
#define SQR_TOOM3_THRESHOLD 360
#define SQR_TOOM4_THRESHOLD 978
#define SQR_TOOM8_THRESHOLD 978
#define DIVREM_1_NORM_THRESHOLD 0 /* always */
#define DIVREM_1_UNNORM_THRESHOLD 38
#define MOD_1_NORM_THRESHOLD 0 /* always */
#define MOD_1_UNNORM_THRESHOLD 0 /* always */
#define USE_PREINV_DIVREM_1 1 /* native */
#define USE_PREINV_MOD_1 1
#define DIVEXACT_1_THRESHOLD 0 /* always */
#define MODEXACT_1_ODD_THRESHOLD 0 /* always (native) */
#define MOD_1_1_THRESHOLD 7
#define MOD_1_2_THRESHOLD 7
#define MOD_1_3_THRESHOLD 10
#define DIVREM_HENSEL_QR_1_THRESHOLD 23
#define RSH_DIVREM_HENSEL_QR_1_THRESHOLD 8
#define DIVREM_EUCLID_HENSEL_THRESHOLD 10
#define MUL_FFT_FULL_THRESHOLD 2016
#define SQR_FFT_FULL_THRESHOLD 2240
#define MULLOW_BASECASE_THRESHOLD 0 /* always */
#define MULLOW_DC_THRESHOLD 274
#define MULLOW_MUL_THRESHOLD 2937
#define MULMID_TOOM42_THRESHOLD 28
#define MULHIGH_BASECASE_THRESHOLD 4
#define MULHIGH_DC_THRESHOLD 49
#define MULHIGH_MUL_THRESHOLD 122
#define MULMOD_2EXPM1_THRESHOLD 18
#define DC_DIV_QR_THRESHOLD 50
#define INV_DIV_QR_THRESHOLD 2444
#define INV_DIVAPPR_Q_N_THRESHOLD 50
#define DC_DIV_Q_THRESHOLD 31
#define INV_DIV_Q_THRESHOLD 6798
#define DC_DIVAPPR_Q_THRESHOLD 11
#define INV_DIVAPPR_Q_THRESHOLD 18575
#define DC_BDIV_QR_THRESHOLD 62
#define DC_BDIV_Q_THRESHOLD 16
#define BINV_NEWTON_THRESHOLD 8
#define REDC_1_TO_REDC_N_THRESHOLD 38
#define ROOTREM_THRESHOLD 6
#define MATRIX22_STRASSEN_THRESHOLD 27
#define HGCD_THRESHOLD 111
#define HGCD_APPR_THRESHOLD 50
#define HGCD_REDUCE_THRESHOLD 6852
#define GCD_DC_THRESHOLD 427
#define GCDEXT_DC_THRESHOLD 270
#define JACOBI_BASE_METHOD 2
#define GET_STR_DC_THRESHOLD 15
#define GET_STR_PRECOMPUTE_THRESHOLD 24
#define SET_STR_DC_THRESHOLD 644
#define SET_STR_PRECOMPUTE_THRESHOLD 1103
#define FAC_DSC_THRESHOLD 422
#define FAC_ODD_THRESHOLD 54
/* fft_tuning -- autogenerated by tune-fft */
#define FFT_TAB \
{ { 4, 3 }, { 3, 2 }, { 2, 1 }, { 1, 1 }, { 1, 0 } }
#define MULMOD_TAB \
{ 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1 }
#define FFT_N_NUM 11
#define FFT_MULMOD_2EXPP1_CUTOFF 128
/* Tuneup completed successfully, took 134 seconds */
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 61
model name : Intel(R) Core(TM) i5-5200U CPU @ 2.20GHz
stepping : 4
microcode : 0x12
cpu MHz : 1941.671
cache size : 3072 KB
physical id : 0
siblings : 4
core id : 0
cpu cores : 2
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 20
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov
pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb
rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology
nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2
ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt
tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch epb
intel_pt tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 avx2
smep bmi2 erms invpcid rdseed adx smap xsaveopt dtherm ida arat pln pts
bugs :
bogomips : 4389.51
clflush size : 64
cache_alignment : 64
address sizes : 39 bits physical, 48 bits virtual
power management:
processor : 1
vendor_id : GenuineIntel
cpu family : 6
model : 61
model name : Intel(R) Core(TM) i5-5200U CPU @ 2.20GHz
stepping : 4
microcode : 0x12
cpu MHz : 851.039
cache size : 3072 KB
physical id : 0
siblings : 4
core id : 1
cpu cores : 2
apicid : 2
initial apicid : 2
fpu : yes
fpu_exception : yes
cpuid level : 20
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov
pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb
rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology
nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2
ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt
tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch epb
intel_pt tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 avx2
smep bmi2 erms invpcid rdseed adx smap xsaveopt dtherm arat pln pts
bugs :
bogomips : 4389.51
clflush size : 64
cache_alignment : 64
address sizes : 39 bits physical, 48 bits virtual
power management:
processor : 2
vendor_id : GenuineIntel
cpu family : 6
model : 61
model name : Intel(R) Core(TM) i5-5200U CPU @ 2.20GHz
stepping : 4
microcode : 0x12
cpu MHz : 799.992
cache size : 3072 KB
physical id : 0
siblings : 4
core id : 0
cpu cores : 2
apicid : 1
initial apicid : 1
fpu : yes
fpu_exception : yes
cpuid level : 20
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov
pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb
rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology
nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2
ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt
tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch epb
intel_pt tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 avx2
smep bmi2 erms invpcid rdseed adx smap xsaveopt dtherm arat pln pts
bugs :
bogomips : 4389.51
clflush size : 64
cache_alignment : 64
address sizes : 39 bits physical, 48 bits virtual
power management:
processor : 3
vendor_id : GenuineIntel
cpu family : 6
model : 61
model name : Intel(R) Core(TM) i5-5200U CPU @ 2.20GHz
stepping : 4
microcode : 0x12
cpu MHz : 2200.085
cache size : 3072 KB
physical id : 0
siblings : 4
core id : 1
cpu cores : 2
apicid : 3
initial apicid : 3
fpu : yes
fpu_exception : yes
cpuid level : 20
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov
pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb
rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology
nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2
ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt
tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch epb
intel_pt tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 avx2
smep bmi2 erms invpcid rdseed adx smap xsaveopt dtherm arat pln pts
bugs :
bogomips : 4389.51
clflush size : 64
cache_alignment : 64
address sizes : 39 bits physical, 48 bits virtual
power management:
