Carl,
Do you have a link to your project? I'm finishing up an MSP430 core
built using a custom high level synthesis language. The core is built
using internal latency insensitive channels and is planned to be put
into a multi-threaded, multi-core setup. I'd like to compare the area/
performance of your core design if possible.
Thanks,
Greg
On Aug 19, 2008, at 12:17 AM, Carl Hakenäs wrote:
Hello,
First, the mspgcc is a great project! Really nice!
I need my mspgcc to compile for a custom RAM/ROM size and hopefully
also custom addresses for rom&ram.
I have tried to experiment with the __data_start and __stack but i
cant make it work.
I would like to compile for a device with 5kb of RAM and 5kb of ROM.
The reason I would like to do this is because I have implemented the
MSP430 in an FPGA using VHDL and I would like to run the dhrystone
program but this requires about 5kb RAM and ROM.
I could compile for a device with lots of RAM but then the ROM file
will be huge.
Also, if I could change the location of RAM and ROM it would be
really good.
The FPGA-implementation might be at opencores.org for public download.
// Carl
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