Hi Greg, That sounds interesting! What language have you used? I have very little knowledge of high level HDL. Also, i am not familiar with the concept latency, insensitive channels. I have also thougt about putting my cores into a multicore platform, however this is only on a planning stage.
You are more than welcome to look at my project, I havent tested it enough and I am not sure if it is 100% bugfree. There are some issues in the MSP430 architecture that i havent understood 100% yet. Some parts of my HDL is also quite crappy written and I havent figured out a good way of writing somestuff. I will try to run the dhrystone program and fix any bug that might occur, then I will upload it to opencores.org. Later on if i have the time I will optimize the design. But, for now I have a design that successfully can calculate the first 100 prime numbers using emulated division. It is a 2stage pipelined design, and the regbank is built from onboard distrubuted ram. RAM and ROM are in BRAM. For some instructions a state machine is used (PUSH/CALL). When an operand needs to be fetched from memory the pipeline is stalled. Here are the synthesis results for a system with cpu, 4k ram and 16k rom. Some glue logic is needed for the RAM/ROM multiplexing. The deviceis a Xilinx XC3S200 (Spartan 3) LUTs: 1022 (27%) MaxF: 69 MHz Is there anything else you would like to know? So, I will send you a link in a few days, is that ok? // Carl On 8/19/08, Greg Hoover <[email protected]> wrote: > Carl, > > Do you have a link to your project? I'm finishing up an MSP430 core > built using a custom high level synthesis language. The core is built > using internal latency insensitive channels and is planned to be put > into a multi-threaded, multi-core setup. I'd like to compare the area/ > performance of your core design if possible. > > Thanks, > Greg > > On Aug 19, 2008, at 12:17 AM, Carl Hakenäs wrote: > > > Hello, > > > > First, the mspgcc is a great project! Really nice! > > > > I need my mspgcc to compile for a custom RAM/ROM size and hopefully > > also custom addresses for rom&ram. > > I have tried to experiment with the __data_start and __stack but i > > cant make it work. > > I would like to compile for a device with 5kb of RAM and 5kb of ROM. > > > > The reason I would like to do this is because I have implemented the > > MSP430 in an FPGA using VHDL and I would like to run the dhrystone > > program but this requires about 5kb RAM and ROM. > > I could compile for a device with lots of RAM but then the ROM file > > will be huge. > > > > Also, if I could change the location of RAM and ROM it would be > > really good. > > > > The FPGA-implementation might be at opencores.org for public download. > > > > // Carl > > > > ------------------------------------------------------------------------- > > This SF.Net email is sponsored by the Moblin Your Move Developer's > > challenge > > Build the coolest Linux based applications with Moblin SDK & win > > great prizes > > Grand prize is a trip for two to an Open Source event anywhere in > > the world > > http://moblin-contest.org/redirect.php?banner_id=100&url=/ > > _______________________________________________ > > Mspgcc-users mailing list > > [email protected] > > https://lists.sourceforge.net/lists/listinfo/mspgcc-users > > > ------------------------------------------------------------------------- > This SF.Net email is sponsored by the Moblin Your Move Developer's challenge > Build the coolest Linux based applications with Moblin SDK & win great prizes > Grand prize is a trip for two to an Open Source event anywhere in the world > http://moblin-contest.org/redirect.php?banner_id=100&url=/ > _______________________________________________ > Mspgcc-users mailing list > [email protected] > https://lists.sourceforge.net/lists/listinfo/mspgcc-users >
