CPU18 is even more unlikely than I thought, and can probably be accommodated with a peephole rule in the compiler for sequences that involve a bis_status_register intrinsic call followed by a normal function call. Except to preserve any existing legacy behavior, I don't think the assembler should be changing what it was told to assemble.
Peter /* CPU18: LPM instruction can corrupt PC/SR registers * * The PC and SR registers have the potential to be corrupted when: * - An instruction using register, absolute, indexed, indirect, * indirect auto-increment, or symbolic mode is used to set the * LPM bits (for example, BIS &xyh, SR). * and * - This instruction is followed by a CALL or CALLA instruction. * * Upon servicing an interrupt service routine, the program counter * (PC) is pushed twice onto the stack instead of the correct * operation where the PC, then the SR registers are pushed onto the * stack. This corrupts the SR and possibly the PC on RETI from the * ISR. * * Workaround: * - Insert a NOP or __no_operation() intrinsic function between the * instruction to enter low-power mode and the CALL or CALLA * instruction. */ ERRATUM_CPU18 = 18, /* UNHANDLED */ ------------------------------------------------------------------------------ Cloud Services Checklist: Pricing and Packaging Optimization This white paper is intended to serve as a reference, checklist and point of discussion for anyone considering optimizing the pricing and packaging model of a cloud services business. Read Now! http://www.accelacomm.com/jaw/sfnl/114/51491232/ _______________________________________________ Mspgcc-users mailing list Mspgcc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/mspgcc-users
