> On Apr 14, 2023, at 6:03 AM, STEFFAN DIEDRICHSEN > <0000009333a9e91c-dmarc-requ...@lists.columbia.edu> wrote: > > >> On 14. Apr 2023, at 06:53, B.J. Buchalter <b...@mhlabs.com> wrote: >> >>> Back then it was an impressive workhorse with low power consumption, using >>> a 40 bit floating point format, if needed. >> >> Isn’t that the SHARC? > > No, look here: > https://urldefense.proofpoint.com/v2/url?u=https-3A__docs.rs-2Donline.com_30f2_0900766b800310c3.pdf&d=DwIFaQ&c=009klHSCxuh5AI1vNQzSO0KGjl4nbi2Q0M1QLJX9BeE&r=TRvFbpof3kTa2q5hdjI2hccynPix7hNL2n0I6DmlDy0&m=RVU8quMLTXvFegXoX5Z0n-podLK7L6H_a44m4Q-t2-4c2ef16TJ4aJ7H-0OF6ZBQ&s=EjgoYP14BpfmFLE4RvBxGk7FcUIGXBgqBiBCVM_jFic&e= > > > For 40 bit floats, you need 2 loads and 2 stores, because the then 32 bit > mantissa needs to be stored in an additional location as an integer. I didn’t > use that.
>> The SHARC definitely had support for 40-bit float (which was very cool - we >> used the heck out of it) but I though the TI floating point DSPs only >> supported 32-bit/64-bit float but no 40-bit float. > > Maybe later version, the C30 was the first FP DSP from TI. Later version like > the TMS320C6xxxx are quite different, but impressive. Ah. Sorry. I guess I never looked at that part. The SHARC had busses and memory organization that actually supported that datatype with single-cycle fetches (for 2 operands IIRC, but it was definitely at least 1 40-bit and one 32-bit at the same time). We used that 40-bit datatype extensively. B.J. Buchalter Metric Halo https://urldefense.proofpoint.com/v2/url?u=http-3A__www.mhlabs.com&d=DwIFaQ&c=009klHSCxuh5AI1vNQzSO0KGjl4nbi2Q0M1QLJX9BeE&r=TRvFbpof3kTa2q5hdjI2hccynPix7hNL2n0I6DmlDy0&m=RVU8quMLTXvFegXoX5Z0n-podLK7L6H_a44m4Q-t2-4c2ef16TJ4aJ7H-0OF6ZBQ&s=OXKy8JUbb4-scSOBIwWOHBJRGhDX2KRPbvoK-zgc4DE&e=
