Hi DSPers,
searching for interesting computer hardware I ended up at one of the important junctions
of DSP machine design: apart from available memory size and MIPS/FLOPS: how much bandwidth
is available to communicate with the various memories involved in for instance a virtual
synthesizer design, or between DSP cores: how much data and control can be communicated
per second, and as secondary question: how big must the communication chunks be ?
In PC design for music applications, I'm sure it can pay to involve the various bandwidths
in the machine in a design, including the free bandwidth like after considering the
instruction pre-fetcher running into SDRAM instead of some level of cache memory for
instance. Probably (usually automatic) cache management and granularity (use big buffers)
are important factors in getting good bandwidth between various computation parts.
For DIY projects, I used to count on say about 50MHz or something in that range max for a
normal wire. But of course a lot of chips, certainly memory chips, could communicate a lot
faster than that with FPGA or DSP IO pins, but getting communication bandwidth of an
appreciable number of hundreds of mega-bits or more per connected wire may not be easy to
get to work reliably, maybe unless you're making a pro-grade printed circuit board for a
project. My Blackfin DSP experiments of a decade ago (multi delay, analog simulation
synth) of connecting up FPGA/CPLD with the system bus of the DSP running at 500/600MHz led
to a bus connection speed of a 100M/s IIRC, but a lot of starter kits, development boards
and available memory and DSP chips cannot easily be connected up to escape, let's call it
micro processor hobby speeds...
Then there's the latest things I've worked on with the Zynq ARM/FPGA that has wonderful
communication bandwidth between the (in my case 2) ARM cores and the programmable logic,
which can connect to the outside world with a lot of external FPGA IO pins. But: not at
gigabit level (requires more expensive FPGA). And as it is I can easily program and
connect up a AXI-lite ARM-bus interface to for instance communicate sample data from giga
memory to the FPGA processing structures, but the disadvantage is that gives about 12
MByte/s bandwidth, which isn't very much compared to the harder to achieve (and there
aren't examples I've found easy enough to follow) DMA based bandwidths the bus and memory
interfaces promise.
How is your experience, any better ?
T. V.
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