Nice board. I'm curious why the blanking pin on the HV5530 isn't working. Is it that you dont see any dimming, or is it something else ? Be careful about the setting of the POL pin; if it's at the wrong level you will turn on all cathodes when you attempt to blank the displays.
I'm working on a 14-tube IN-18 clock that uses the HV5530, and I plan to use the blanking pin for dimming. My control logic is entirely FPGA, so I have no issues about software timing, etc. Although it's inefficient, you could implement a lower-speed PWM by sending alternate serial packets with all cathodes off, then the desired cathodes on, etc. I dont know if your CPU can handle that workload under software control, though. The datasheet parameters dont specify a *minimum* propagation delay on the DataOut pin (tDLH), and there is a minimum hold-time requirement on the DataIn pin, so it's theoretically not possible to cascade these devices unless you alternately invert the CLK signal or add delay on the DataIn pin. This wont cause a problem with blanking, but it could cause marginal operation. I chose to alternately invert the CLK signal. -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to neonixie-l+unsubscr...@googlegroups.com. To post to this group, send an email to neonixie-l@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/e3d9e96a-1b3b-4c43-95dd-2a0eaa38c52d%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
