I took another look at the level-translator circuit, and I noticed there is a resistive pulldown (10K). This could be the problem, but without any scope traces I cant be certain. You could do a SPICE simulation and get a decent idea what the timing is.
The CLK on the HV5622 is falling-edge, and with a resistive pulldown it will have a slow edge-rate. The datasheet does not specify an input-capacitance, but it's probably around 10pF. With two HV5622 devices and the 10K pulldown, the time-constant is on the order of 200nsec. I've seen two kinds of timing problems with slow edge-rates. 1. Noise susceptibility. With a slow clock-edge, any noise that occurs while the clock is near the threshold point can cause an extra clock edge (ie, a glitch). 2. Timing-skew. Each component will have a slightly different threshold voltage (the point where it distinguishes a '1' from a '0'). With a slow clock-edge, the difference in threshold-voltage (dv) causes a timing-difference (dt). A slow clock-edge has a low dv/dt, and you can actually calculate the timing-uncertainty if you know the variation in threshold voltage. The risk here is that the first HV5622 clocks slightly 'early', and the second one clocks slightly 'late'. If that happens, the serial data being shifted will skip a bit. This is a hold-time violation and also called 'shoot-thru'. One option as you said is to use an IC level-translator. A possible quick-and-dirty option is to change the circuit so it uses an NPN pulldown, rather than a resistor. If you go that route, you should change the PNP pullup to a resistor unless you carefully simulate the circuit and optimize the design. If you dont optimize, you will get 'crowbar' current between the +12V supply and GND while both transistors are on, and that will create tons of noise at the worst possible time -- when your clock is changing. (Trust me, I've designed I/O pads on ICs before....). You should be able to get-by with a slow rising-edge on the clock line (remember: the HVxxx device is using the falling-edge, not the rising edge) *as long as you dont have any noise*. Any significant noise will cause another clock-glitch. The other signals (LE, DATA) dont need "clean" edges as long as you provide enough setup and hold margin, so you can keep the level-shifter as-is for these signals. -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to neonixie-l+unsubscr...@googlegroups.com. To post to this group, send an email to neonixie-l@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/bf68d1f4-cc00-430c-a6bd-73f26b982202%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
