On Sat, Mar 17, 2018 at 05:28:47PM +0800, Chen-Yu Tsai wrote: > From: Icenowy Zheng <icen...@aosc.io> > > There's a GMAC configuration register, which exists on A64/A83T/H3/H5 in > the syscon part, in the CCU of R40 SoC. > > Export a regmap of the CCU. > > Read access is not restricted to all registers, but only the GMAC > register is allowed to be written. > > Signed-off-by: Icenowy Zheng <icen...@aosc.io> > Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Gah, this is crazy. I'm really starting to regret letting that syscon in in the first place... And I'm not really looking forward the time where SCPI et al. will be mature and we'll have the clock controller completely outside of our control. Maxime -- Maxime Ripard, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com
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