From: "Williams, Mitch A" <[EMAIL PROTECTED]>
Date: Fri, 6 Jul 2007 10:14:56 -0700

> In my opinion, IOMMU table locking is the major issue with this type of
> architecture.  Since both Intel and AMD are touting IOMMUs for virtual-
> ization support, this is an issue that's going to need a lot of
> scrutiny.

For the allocation of IOMMU entries themselves you can play tricks
using atomic operations on 64-bit words of the allocator bitmap
to avoid locking that.

You can use per-cpu salts to determine where to start the search
and avoid hitting the same cachelines as other cpus working on
the same table.

But you'll need to lock in order to flush the IOMMU tlb I'm afraid.
The way to mitigate that is to only flush the IOMMU tlb once per
allocator generation.
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