David Woodhouse <dw...@infradead.org> :
[...]
> Did you ever work this out ?
Not specifically.
> I'm seeing something similar on the inward -facing interface on my home
> router under high load — and it doesn't automatically recover.
[...]
> [308309.457239] Pid: 0, comm: swapper Not tainted 3.7.1 #1
It's unrelated but you may have already noticed
7fe0ee099ad5e3dea88d4ee1b6f20246b1ca57c3 ("net: 8139cp: fix a BUG_ON
triggered by wrong bytes_compl").
[...]
> [308309.574551] 8139cp 0000:00:0b.0 eth1: Transmit timeout, status c 2b
> 0 80ff
Rx and Tx are enabled.
Instant (untested) hack below.
diff --git a/drivers/net/ethernet/realtek/8139cp.c
b/drivers/net/ethernet/realtek/8139cp.c
index d79e33b..09ee6fd 100644
--- a/drivers/net/ethernet/realtek/8139cp.c
+++ b/drivers/net/ethernet/realtek/8139cp.c
@@ -129,6 +129,9 @@ MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum
number of filtered mu
/* Time in jiffies before concluding the transmitter is hung. */
#define TX_TIMEOUT (6*HZ)
+/* TODO: calibrate. It ought to be related to the PCI bus frequency. */
+#define CP_EARLY_TIMEOUT (8 * 1024)
+
/* hardware minimum and maximum for a single frame's data payload */
#define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
#define CP_MAX_MTU 4096
@@ -146,9 +149,11 @@ enum {
TxConfig = 0x40, /* Tx configuration */
ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
RxConfig = 0x44, /* Rx configuration */
+ TimerCount = 0x48, /* 32 bit general purpose timer. */
RxMissed = 0x4C, /* 24 bits valid, write clears */
Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
Config1 = 0x52, /* Config1 */
+ TimerInt = 0x54, /* TimerCount IRQ triggering timeout value */
Config3 = 0x59, /* Config3 */
Config4 = 0x5A, /* Config4 */
MultiIntr = 0x5C, /* Multiple interrupt select */
@@ -283,7 +288,8 @@ enum {
LANWake = (1 << 1), /* Enable LANWake signal */
PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
- cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
+ cp_norx_intr_mask = PciErr | TimerIntr | LinkChg |
+ TxOK | TxErr | TxEmpty,
cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
};
@@ -608,6 +614,15 @@ static irqreturn_t cp_interrupt (int irq, void
*dev_instance)
if (status & (TxOK | TxErr | TxEmpty | SWInt))
cp_tx(cp);
+
+ if ((status & TimerIntr) && (cp->tx_head != cp->tx_tail)) {
+ if (net_ratelimit()) {
+ netdev_info(dev, "Timeout head=%08x, tail=%08x\n",
+ cp->tx_head, cp->tx_tail);
+ }
+ cp_tx(cp);
+ }
+
if (status & LinkChg)
mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
@@ -885,6 +900,8 @@ static netdev_tx_t cp_start_xmit (struct sk_buff *skb,
out_unlock:
spin_unlock_irqrestore(&cp->lock, intr_flags);
+ cpw32(TimerCount, CP_EARLY_TIMEOUT);
+
cpw8(TxPoll, NormalTxPoll);
return NETDEV_TX_OK;
@@ -1064,6 +1081,8 @@ static void cp_init_hw (struct cp_private *cp)
cpw16(MultiIntr, 0);
+ cpw32(TimerInt, CP_EARLY_TIMEOUT);
+
cpw8_f(Cfg9346, Cfg9346_Lock);
}
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