Add the FSP (Firmware System Processor) falcon engine type that will handle secure boot and Chain of Trust operations on Hopper and Blackwell architectures.
The FSP falcon replaces SEC2's role in the boot sequence for these newer architectures. This initial stub just defines the falcon type and its base address. Signed-off-by: John Hubbard <[email protected]> --- drivers/gpu/nova-core/falcon.rs | 1 + drivers/gpu/nova-core/falcon/fsp.rs | 31 +++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 drivers/gpu/nova-core/falcon/fsp.rs diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs index 37bfee1d0949..a0cfb4442df1 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -33,6 +33,7 @@ regs::macros::RegisterBase, // }; +pub(crate) mod fsp; pub(crate) mod gsp; mod hal; pub(crate) mod sec2; diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/falcon/fsp.rs new file mode 100644 index 000000000000..cc3fc3cf2f6a --- /dev/null +++ b/drivers/gpu/nova-core/falcon/fsp.rs @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! FSP (Firmware System Processor) falcon engine for Hopper/Blackwell GPUs. +//! +//! The FSP falcon handles secure boot and Chain of Trust operations +//! on Hopper and Blackwell architectures, replacing SEC2's role. + +use crate::{ + falcon::{ + FalconEngine, + PFalcon2Base, + PFalconBase, // + }, + regs::macros::RegisterBase, +}; + +/// Type specifying the `Fsp` falcon engine. Cannot be instantiated. +pub(crate) struct Fsp(()); + +impl RegisterBase<PFalconBase> for Fsp { + // FSP falcon base address for Blackwell + const BASE: usize = 0x8f2000; +} + +impl RegisterBase<PFalcon2Base> for Fsp { + const BASE: usize = 0x8f3000; +} + +impl FalconEngine for Fsp { + const ID: Self = Fsp(()); +} -- 2.52.0
