On Thu, 03 Feb 2005 10:23:03 +0100
Erik Hofman <[EMAIL PROTECTED]> wrote:
> >>> What's the demand anyhow? If PCIX is also 64-bit, and there's demand
> >>> for that, we could meet in the middle just support PCI64/66.
> >>
> >> I think PCIX is 64bit, isn't it? That would be a nice trade off.
>From the pci-x addendum to the pci standard:
----
The PCI-X definition introduces several major enhancements that enable faster
and more
efficient data transfers:
1. Higher clock frequencies up to 133 MHz1.
2. Signaling protocol changes to enable registered outputs and inputs, that is,
device
outputs that are clocked directly out of a register and device inputs that
are clocked
directly into a register. The protocol is restricted such that devices
have two clocks
to respond to any input changes.
3. New information passed with each transaction that enables more efficient
buffer
management schemes.
Each transaction in a Sequence (see definition in Section 1.2)
identifies the total
number of bytes remaining to be read or written. If a transaction is
disconnected,
the new transaction that continues the Sequence contains an updated
remaining
byte count.
Each transaction includes the identity of the initiator (bus number,
device
number, and function number) and the transaction sequence (or
ÂÃthreadÂÃ) to
which it belongs (Tag).
Additional information about transaction ordering and cacheability
requirements.
4. Restricted wait state and disconnection rules optimized for more efficient
use of the
bus and memory resources.
Initiators are not permitted to insert wait states.
Targets are not permitted to insert wait states after the initial
data phase.
Both initiators and targets are permitted to end a burst transaction
only on
naturally aligned 128-byte boundaries. This encourages longer bursts
and
enables more efficient use of cacheline-based resources such as the
host bus and
main memory. Targets are also permitted to disconnect transactions
after only a
single data phase in address ranges where longer transactions are not
necessary.
5. Delayed Transactions in conventional PCI replaced by Split Transactions in
PCI-X.
All transactions except memory write transactions must be completed
immediately or
they must be completed using Split Transaction protocol. In Split
Transaction
protocol, the target terminates a transaction by signaling Split Response,
executes the
command, and initiates its own Split Completion transaction to send the
data or a
completion message back to the original initiator.
6. A wider range of error recovery implementations for PCI-X devices that reduce
system intervention on data parity errors.
PCI-X requirements are defined in many cases to be the same or similar to their
corresponding conventional PCI requirements. This simplifies the task of
converting
conventional designs to PCI-X and of making PCI-X devices that work in
conventional
environments.
In most cases, this document does not repeat specifications that remain
unchanged from
PCI 2.2, Bridge 1.1, PCI PM 1.1, and PCI HP 1.0. Any requirement not specified
to be
different for PCI-X devices remains the same as specified in these other
specifications.
The following PCI-X features are some of the features that are the same as
conventional
PCI:
1. Devices have either a 32- or 64-bit data bus.
2. Address and data are multiplexed on the same bus.
3. Transactions have one or two address phases.
4. Transactions have one or more data phases.
5. Devices decode address and command and assert DEVSEL# to claim a transaction.
6. Add-in card mechanical specification.
7. Signal names and connector pin-out (except one new pin, PCIXCAP).
8. Power supply voltages.
9. Maximum power consumption for add-in cards.
10. Single clock signal for all devices and transactions. The bus changes state
and data
transfers on the rising edge of the clock.
11. PCI hot-plug architecture and hot-insertion and hot-removal sequences.
---
If anyone here needs the pci standards drop me a mail, i have them as pdf.
Not to talk that i'm even allowed to copy them (isn't copyrigt a nice thing ? :)
Attila Kinali
--
éãåããéãåã
_______________________________________________
Open-graphics mailing list
[email protected]
http://lists.duskglow.com/mailman/listinfo/open-graphics
List service provided by Duskglow Consulting, LLC (www.duskglow.com)
