Ok, here's my resolution at this point.  I'm going to design basic
logic blocks to run as close to 200MHz as I can get.  But how fast the
timing analyzer says something will go when it's all by its lonesome
and how fast it goes when it's mixed with gobs of other logic are two
different animals.  Routing will MURDER your design.  :)  As such,
we'll just take what we can get.

However, I also resolve to change a few ideas I have about how I was
going to implement the design.  For instance, if I can, I'll make the
two texture units independent.  This way, two textures can be about as
fast as a single texture.  As such, the design will be "slow" if you
have it doing simple things, but you can keep adding complexity
without slowing it down.

I'm still trying to get the adder to 200MHz.  I currently have it at
about 7.5 ns (about 133MHz), but it's 6 pipeline stages.  I had it
down to five stages at 100MHz.  If I can get it down to 5 ns, we might
be able to get it to run at 6ns in the final design.  Squeezing out
those last few ns isn't easy.
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