On Mon, 21 Feb 2005 23:31:02 +0100
Nicolas Boulay <[EMAIL PROTECTED]> wrote:
> You don't plan to tape out an asic by end of june ?!
I think Timothy knows what he is doing.
> The fpga board could help debugging, and if you're lucky asic could be ready
> for decembre.
Does it really take half a year from tape out to series production ?
I thought that was in the 3-4 months range ?
But anyways, this leads to the next question of a project schedule.
This isn't an OSS but a busines project, thus we should all agree
on a somewhat tight schedule until when we want to have certain
things finished.
> But don't forget, the debugging that need to be done. Software model did not
> replace engenering model.
C is not VHDL/Verilog :)
Attila Kinali
--
éãåããéãåã
_______________________________________________
Open-graphics mailing list
[email protected]
http://lists.duskglow.com/mailman/listinfo/open-graphics
List service provided by Duskglow Consulting, LLC (www.duskglow.com)
