On Tuesday 05 April 2005 19:31, Andr� Pouliot wrote: > It sure would be nice if it cost be the lowest possible. And the fact > that the PCI interface will be in a CPLD have some draw back for the > cost, the opportunity to code a pci interface and transmission delay > between the CPLD and FPGA. It do have the advantage for the pci bus > that the device doesn't dissaspear suddently and if the programation > fail your still able to upload new code. That said, the fact the > product is going to asic the FPGA card not having the CPLD would not > be a great dissavantage since most of the people buying the prototype > card would have or be able to build a JTAG cable > www.*xilinx*.com/support/programr/*jtag*_*cable*.pdf
I have one actually. I've been waiting for a chance to use it. > For the debugging feature as I see it there's only some necessary : a > lot of header for signal test point something like two 40 pins > headers and the jtag header. For the last part, sorry to dissapoint > you Daniel ;), but I like my board to have at less 2 led, one to > signal when programing and one for a visual watchdog. ;) Regards, Daniel _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
