On 6/14/06, Isaac Gravestock <[EMAIL PROTECTED]> wrote:
First off I'd like to say this is a fantastic idea. I don't know
anything about verilog or VHDL so I think I'll be a good test case.
It's pretty clear, just a couple questions:
We'll have to see how to incorporate this into official lessons....
> You can have multi-bit wires:
>
> wire [3:0] c;
Can you explain why there are 2 values (3 and 0) and what they mean?
We're specifying a range of bits. The two numbers are the left and
right ends of the range. So given [3:0], you have specified that
there will exist bits 3, 2, 1, and 0 in the bus named "c".
Order matters, so if you used [0:3], then bit zero would be the most
significant bit when doing math.
>Given a wire, you can select individual bits, which is to say that you
>can pick out a bit from a vector of bits:
>
> wire g;
> assign g = f[2]; // assign bit 2 of f to g;
How come you only needed to specify one value here (f[2] rather than
f[2:0] or something)?
In this case, we're just selecting one of the bits. We can think of f
as an array of bits, and [2] is an index. If we were to specify
[2:0], we'd be asking for a bit slice, which is a sub range of bits in
f.
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