On 6/14/06, Vinicius Santos <[EMAIL PROTECTED]> wrote:
On 6/13/06, Timothy Miller <[EMAIL PROTECTED]> wrote:
> You can also have arrays of wires (in most dialects of Verilog):
>
> wire [7:0] k [0:20]; // An array of twenty-one 8-bit busses
How about acessing the array? The same way we declare it? Like:
wire a = [5]k[11]; // asign the (5+1)th bit of the (11+1)th bus to a
wire [7:0] b= k[2]; // asign the (2+1)th bus to the b 8-bit bus
wire [0:20] c = [2] k; // asign the third bit of every bus to the 21-bit bus
Is that correctly?
You make an excellent point about something I left out. No, I'm
afraid it's less capable than that.
Given the array
wire [7:0] k [0:20];
You can access elements of the array:
wire [7:0] m = k[x]; // x is a constant or another signal
In this case, we're selecting the entry in the memory, and that entry
is 8 bits. As it turns out, there's no way to do a bit-select on a
memory select, so "k[x][y]" is not valid. In this case, you'd have to
assign to an intermediate signal:
wire n = m[2]; // Now we have bit 2 of entry x of k.
What's more important here is that you cannot assign to an individual
bit, just array elements:
assign k[3] = w; // Associating an 8-bit value in entry 3 of memory k
Where this becomes important really is when we're working with regs
later. Wire arrays aren't really memories. I've used them on
occasion when it was convenient to assign data one way and then
multiplex it out another.
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