On 3/4/07, Timothy Normand Miller <[EMAIL PROTECTED]> wrote:
There are a number of different kinds of Verilog code blocks we'd
write, including:
(1) Simulation prototypes of something we want to synthesize
(2) Synthesizable version of (1)
(3) Test harnesses specifically for (1) and (2)
(4) Library code that's generally useful for all sorts of different situations
In general, for a specific block, like the video controller, I'd like
to keep (1), (2), and (3) in basically the same place, although it may
be sensible in many cases to have subdirectories that contain these
different pieces. I think this would keep things coherent. Related
items go together, and you can think of the pieces as a project unto
themselves.
I agree that they should be in roughly the same directory (maybe with
a tests subdir), but I was thinking separate files, so that files
containing (2) can be simulated without any manipulation from initial
blocks that aren't part of the test code.
I'm getting further behind on things, unfortulately, so your patch is
slipping further down my list of emails. This is why I'd like to give
you write access. What are the general nature of your changes?
not very significant for now:
- added a Makefile to the test directory to make it easier to manage
tests later on
- added a 32x32.hex target to drivers/lib/video_controller
- renamed RAMB16_S36_36.v to RAMB16_S36_S36.h
- moved $readmemh from RAMB16_S36_S36.v to tests/video_test.v, based
on the above opinion
- changed the name of the dump file in video_test.v
- deleted the initial block from vid_control.v - I grepped for it in
the whole tree and it seems unused, plus it's possible to just use the
configuration register to modify that output anyway.
I've attached a patch, but again, don't spend time applying it if
you're busy. I plan to actually write some tests, but that won't be
for another week, I think. Also, in all honesty, it's probably not a
good idea to accept any changes from me without reviewing them,
considering how little experience I have with hardware development.
Index: rtl/vid_ctl/test/video_test.v
===================================================================
--- rtl/vid_ctl/test/video_test.v (revision 141)
+++ rtl/vid_ctl/test/video_test.v (working copy)
@@ -5,7 +5,7 @@
initial begin
- $dumpfile( "test.vcd" );
+ $dumpfile( "video_test.vcd" );
$dumpvars;
reset = 0; // assert
@@ -46,9 +46,9 @@
wire req_enq;
wire req_busy = 0;
- wire [255:0] fifo_data;
-
+wire [255:0] fifo_data;
+
// video out
wire [0:127] out_pixels;
wire [2:0] out_signals;
@@ -57,6 +57,7 @@
initial begin
reg_write = 0;
+ $readmemh("../../../drivers/lib/video_controller/32x32.hex", vc.dlist_ram.mem, 0);
end
Index: rtl/vid_ctl/test/pixel_send_test.v
===================================================================
--- rtl/vid_ctl/test/pixel_send_test.v (revision 141)
+++ rtl/vid_ctl/test/pixel_send_test.v (working copy)
@@ -1,4 +1,4 @@
-module pixel_fetch_test;
+module pixel_send_test;
Index: rtl/vid_ctl/test/Makefile
===================================================================
--- rtl/vid_ctl/test/Makefile (revision 0)
+++ rtl/vid_ctl/test/Makefile (revision 0)
@@ -0,0 +1,22 @@
+#!/usr/bin/make
+
+VCTL_PROGDIR = ../../../drivers/lib/video_controller/
+VPATH = $(VCTL_PROGDIR)
+
+check: video_test
+ for prog in $^; do \
+ ./$$prog; \
+ done;
+
+video_test: 32x32.hex video_test.v dummy_fifo.v
+
+clean:
+ rm -f *.vcd video_test
+
+%:: %.v
+ iverilog -y.. -y. -o $@ -Wall [EMAIL PROTECTED]
+
+32x32.hex:
+ cd $(VCTL_PROGDIR); make 32x32.hex
+
+.PHONY: check,clean
Index: rtl/vid_ctl/RAMB16_S36_36.v
===================================================================
--- rtl/vid_ctl/RAMB16_S36_36.v (revision 141)
+++ rtl/vid_ctl/RAMB16_S36_36.v (working copy)
@@ -1,51 +0,0 @@
-
-
-module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
-
- output [31:0] DOA;
- output [3:0] DOPA;
- reg [31:0] DOA;
- reg [3:0] DOPA;
- input [8:0] ADDRA;
- input [31:0] DIA;
- input [3:0] DIPA;
- input ENA, CLKA, WEA, SSRA;
-
- output [31:0] DOB;
- output [3:0] DOPB;
- reg [31:0] DOB;
- reg [3:0] DOPB;
- input [8:0] ADDRB;
- input [31:0] DIB;
- input [3:0] DIPB;
- input ENB, CLKB, WEB, SSRB;
-
-reg [35:0] mem [0:511];
-initial $readmemh("/home/admin/trunk/drivers/lib/video_controller/32x32.hex", mem, 0);
-
-integer k;
-
-
-always @(posedge CLKA) begin
- if (ENA) begin
- {DOPA, DOA} <= mem[ADDRA];
- if (WEA) begin
- mem[ADDRA] <= {DIPA, DIA};
- end
- end else begin
- {DOPA, DOA} <= 'hx;
- end
-end
-
-always @(posedge CLKB) begin
- if (ENB) begin
- {DOPB, DOB} <= mem[ADDRB];
- if (WEB) begin
- mem[ADDRB] <= {DIPB, DIB};
- end
- end else begin
- {DOPB, DOB} <= 'hx;
- end
-end
-
-endmodule
Index: rtl/vid_ctl/RAMB16_S36_S36.v
===================================================================
--- rtl/vid_ctl/RAMB16_S36_S36.v (revision 141)
+++ rtl/vid_ctl/RAMB16_S36_S36.v (working copy)
@@ -21,7 +21,6 @@
input ENB, CLKB, WEB, SSRB;
reg [35:0] mem [0:511];
-initial $readmemh("/home/admin/trunk/drivers/lib/video_controller/32x32.hex", mem, 0);
integer k;
Index: rtl/vid_ctl/vid_control.v
===================================================================
--- rtl/vid_ctl/vid_control.v (revision 141)
+++ rtl/vid_ctl/vid_control.v (working copy)
@@ -252,16 +252,6 @@
end
end
end
-
-// synopsys translate_off
-initial begin
- #10;
- vid_clk_rst = 1;
- #200;
- vid_clk_rst = 0;
-end
-// synopsys translate_on
-
endmodule
Index: rtl/vid_ctl/makeit
===================================================================
--- rtl/vid_ctl/makeit (revision 141)
+++ rtl/vid_ctl/makeit (working copy)
@@ -1 +1 @@
-iverilog vid_control.v ins_unit.v pixel_fetch.v pixel_send.v RAMB16_S36_36.v
+iverilog vid_control.v ins_unit.v pixel_fetch.v pixel_send.v RAMB16_S36_S36.v
Index: docs/vid_ctl.tex
===================================================================
--- docs/vid_ctl.tex (revision 141)
+++ docs/vid_ctl.tex (working copy)
@@ -172,7 +172,7 @@
{\tt DE} & Value of the Data Enable signal. \tabularnewline
{\tt VSYNC} & Value of the Vertical Sync signal. \tabularnewline
{\tt HSYNC} & Value of the Horizontal Sync signal. \tabularnewline
-{\tt Cursor} & $\bullet$ During blanking, the value {\tt '00'} leaves cursor coordiates
+{\tt Cursor} & $\bullet$ During blanking, the value {\tt '00'} leaves cursor coordinates
unchanged. \\
$\bullet$ During active video, {\tt '00'} advances the cursor X coordinate. \\
$\bullet$ {\tt '01'} increments the cursor Y coordinate and resets X to its initial
@@ -310,7 +310,7 @@
\subsubsection{{\tt ADDR: 6}}
-The 21-bit {\tt Memory\_Address} field is shited left by 7 bits to form a 28-bit memory
+The 21-bit {\tt Memory\_Address} field is shifted left by 7 bits to form a 28-bit memory
address. (Memory addresses always refer to 256-bit words.) This address is taken as
the new value for the current graphics memory pointer where pixels will be fetched
from.
@@ -405,7 +405,7 @@
; depth = depth in bits per pixel
; hfp = duration of HFP in pixels
; hsync = duration of HSYNC in pixels
-; hpb = duration of HBP in pixels
+; hbp = duration of HBP in pixels
; vfp = duration of VFP in scanlines
; vsync = duration of HSYNC in scanlines
; vbp = duration of VBP in scanlines
@@ -415,7 +415,7 @@
; from the framebuffer, skip any padding on the right, and finish off the
; first scanline of the VFP.
000 WAIT Repeat=hsync/4 HSYNC,RESET_CURSOR_XY
-001 WAIT Repeat=hpb/4
+001 WAIT Repeat=hbp/4
002 ADDR vp_addr/128
003 INC vp_addr&0x7f
004 WAIT Repeat=2
Index: drivers/lib/video_controller/Makefile
===================================================================
--- drivers/lib/video_controller/Makefile (revision 141)
+++ drivers/lib/video_controller/Makefile (working copy)
@@ -25,6 +25,9 @@
32x32.o: 32x32.c
$(CC) -c 32x32.c
+32x32.hex: 32x32
+ ./32x32
+
clean:
rm -f *.o *.hex *~
rm -f progressive.c progressive.h test.c test.h 640x480 32x32 test
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