This bit of code is necessary to make the block work right for
simulation. The translate on/off is there to tell the synthesizer to
ignore the code so that we don't get a warning. But it needs to be
there for simulation. In this case, we've removed a bunch of reset
nets and use the global reset in the Xilinx chip. Howard can do a
better job of explaining the details, but this was either the only or
the easiest way to get the circuit to function correctly when the
resets are altered in this way: in simulation only, we force what the
reset signal to behave in the way that it will in the hardware.
So, no. This shouldn't be removed.
On 3/4/07, Simon <[EMAIL PROTECTED]> wrote:
From the diff:
Index: rtl/vid_ctl/vid_control.v
===================================================================
--- rtl/vid_ctl/vid_control.v (revision 141)
+++ rtl/vid_ctl/vid_control.v (working copy)
@@ -252,16 +252,6 @@
end
end
end
-
-// synopsys translate_off
-initial begin
- #10;
- vid_clk_rst = 1;
- #200;
- vid_clk_rst = 0;
-end
-// synopsys translate_on
-
endmodule
So, I interpret that to mean that the rest of the file is intended for
synthesis in some way, based on the comment pragma. I grepped for
anything using that output pin and came up with nothing, so it seems
safe to play with. As far as I understand things, that sort of code
is bad style, someone might forget to test or code for the
initialisation of the pin if they're only testing in a simulator,
since the initial block takes care of it.
And yeah, that memory file is short, at least. As I've said, I don't
really know enough about the code to know where I should be helping at
this point (still planning on writing tests though), but at least I'm
more comfortable with Verilog than I was 2 weeks ago.
--
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Favorite book: The Design of Everyday Things, Donald A. Norman, ISBN
0-465-06710-7
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