Hi Josh, I'm just seeing the end of this thread; but if there is any reason the BiasWorker isn't working it is probably Jim waiting to synchronize with some of our upstream HDL contributions that have nothing to do with the BiasWorker. I'll talk to Jim today - or he will chime in.
-Shep On Tue, Mar 20, 2012 at 2:49 AM, Sutton, Joshua (Contractor) < [email protected]> wrote: > ** > > *UNCLASSIFIED* > Hi Jim, > Just revisiting this. Has there been any progress on getting the hdl > version of the bias worker working? > I'm looking for a simple "out-of-the-box" xml example to test the comms > between the fpga and the cpu. > Cheers, > Josh > > ------------------------------ > *From:* James Kulp [mailto:[email protected]] > *Subject:* Re: [opencpi_dev] FPGA<->RCC example [SEC=UNCLASSIFIED] > > Hi Josh, > > The basic idea is to simply "connect the workers". > There are two ways to do this: > 1. Via the control API (create workers, get their ports, and connect > them). > An example is the canny example, although it has a bunch of OpenCV stuff > that is not relevant. > (See the control API document). > > 2. Via the (recently finally added) XML technique of creating an XML > description of the application and its connections. > An example is bias_xml (biasFile.cxx). Where you could assign the bias > worker (selection set to "model == hdl"). > (Unfortunately this technique is only shown in the various "*_xml" > examples, and not documented yet. > > Probably a this point the xml technique is simplest. > > Both the XML and Control API are agnostic to the type of worker. > > The testRpl program is used to do this too, although it is a somewhat > contorted example. > > There is some glitch that currently prevents the "bias_xml" from working > with the "bias" worker assigned to an FPGA. > > We'll be looking at that shortly. > > Cheers, > > Jim > > > > > > On 1/12/12 9:08 PM, Sutton, Joshua (Contractor) wrote: > > *UNCLASSIFIED* > > Hi, > > Is there an example of how to interface rcc worker(s) with FPGA worker(s) > via the PCI interface? > > Looking to do the typical signal flow chain - ie: > ADC-> FPGA_WORKER -> PCI_BUS -> RCC_WORKER -> FILE I/O -> RCC_WORKER -> > PCI_BUS -> FPGA_WORKER -> DAC > > Cheers, > Josh > > > *IMPORTANT*: This email remains the property of the Department of Defence > and is subject to the jurisdiction of section 70 of the Crimes Act 1914. If > you have received this email in error, you are requested to contact the > sender and delete the email. > > > _______________________________________________ > opencpi_dev mailing > [email protected]http://lists.opencpi.org/listinfo.cgi/opencpi_dev-opencpi.org > > > *IMPORTANT*: This email remains the property of the Department of Defence > and is subject to the jurisdiction of section 70 of the Crimes Act 1914. If > you have received this email in error, you are requested to contact the > sender and delete the email. > > _______________________________________________ > opencpi_dev mailing list > [email protected] > http://lists.opencpi.org/listinfo.cgi/opencpi_dev-opencpi.org > >
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