Icarus Verilog is a multi-purpose tool for simulation and synthesis of Verilog. It is also useful for linting verilog and other tasks.
Signed-off-by: Nathan Rossi <nat...@nathanrossi.com> --- .../icarus-verilog/icarus-verilog_git.bb | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 meta/recipes-devtools/icarus-verilog/icarus-verilog_git.bb diff --git a/meta/recipes-devtools/icarus-verilog/icarus-verilog_git.bb b/meta/recipes-devtools/icarus-verilog/icarus-verilog_git.bb new file mode 100644 index 0000000000..d1e4cfdd33 --- /dev/null +++ b/meta/recipes-devtools/icarus-verilog/icarus-verilog_git.bb @@ -0,0 +1,33 @@ +DESCRIPTION = "Icarus Verilog is a Verilog simulaton and synthesis tool" +HOMEPAGE = "http://iverilog.icarus.com/"; +LICENSE = "GPLv2" +SECTION = "devel/verilog" + +LIC_FILES_CHKSUM = "file://COPYING;md5=b234ee4d69f5fce4486a80fdaf4a4263" + +SRC_URI = "git://github.com/steveicarus/iverilog.git;protocol=https" +SRCREV = "ac87138c44cd6089046668c59a328b4d14c16ddc" + +S = "${WORKDIR}/git" + +PV = "10.2+git${SRCPV}" + +inherit autotools + +EXTRA_OEMAKE_append = ' HOSTCC="${BUILD_CC}" HOSTCFLAGS="${BUILD_CFLAGS}"' + +# issues with install races +PARALLEL_MAKEINST = "" + +# don't regen aclocal or autoheader +EXTRA_AUTORECONF += "--exclude=aclocal --exclude=autoheader" + +DEPENDS = " \ + flex-native bison-native \ + gperf-native \ + readline ncurses \ + " + +FILES_${PN} += "${libdir}/ivl" + +BBCLASSEXTEND = "native nativesdk" -- 2.14.1 -- _______________________________________________ Openembedded-core mailing list Openembedded-core@lists.openembedded.org http://lists.openembedded.org/mailman/listinfo/openembedded-core
